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firelizzard18firelizzard18
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Viable NXP/Teensy support
- Fix UART & putChar - Timer-based sleep - Enable systick in abort - Buffered, interrupt-based UART TX - Use the new interrupt API and fix sleepTicks - Make pins behave more like other boards - Use the MCU's UART numbering - Allow interrupts to wake the scheduler (#1214)
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‎src/machine/board_teensy36.go‎

Lines changed: 92 additions & 83 deletions
Original file line numberDiff line numberDiff line change
@@ -2,91 +2,100 @@
22

33
package machine
44

5-
import (
6-
"device/nxp"
7-
)
8-
9-
// //go:keep
10-
// //go:section .flash_config
11-
// var FlashControl = [16]byte{
12-
// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
13-
// 0xFF, 0xFF, 0xFF, 0xFF, 0xDE, 0xF9, 0xFF, 0xFF,
14-
// }
5+
// CPUFrequency returns the frequency of the ARM core clock (180MHz)
6+
func CPUFrequency() uint32 { return 180000000 }
157

16-
func CPUFrequency() uint32 {
17-
return 180000000
18-
}
8+
// ClockFrequency returns the frequency of the external oscillator (16MHz)
9+
func ClockFrequency() uint32 { return 16000000 }
1910

2011
// LED on the Teensy
21-
const LED Pin = 13
12+
const LED = PC05
13+
14+
// digital IO
15+
const (
16+
D00 = PB16
17+
D01 = PB17
18+
D02 = PD00
19+
D03 = PA12
20+
D04 = PA13
21+
D05 = PD07
22+
D06 = PD04
23+
D07 = PD02
24+
D08 = PD03
25+
D09 = PC03
26+
D10 = PC04
27+
D11 = PC06
28+
D12 = PC07
29+
D13 = PC05
30+
D14 = PD01
31+
D15 = PC00
32+
D16 = PB00
33+
D17 = PB01
34+
D18 = PB03
35+
D19 = PB02
36+
D20 = PD05
37+
D21 = PD06
38+
D22 = PC01
39+
D23 = PC02
40+
D24 = PE26
41+
D25 = PA05
42+
D26 = PA14
43+
D27 = PA15
44+
D28 = PA16
45+
D29 = PB18
46+
D30 = PB19
47+
D31 = PB10
48+
D32 = PB11
49+
D33 = PE24
50+
D34 = PE25
51+
D35 = PC08
52+
D36 = PC09
53+
D37 = PC10
54+
D38 = PC11
55+
D39 = PA17
56+
D40 = PA28
57+
D41 = PA29
58+
D42 = PA26
59+
D43 = PB20
60+
D44 = PB22
61+
D45 = PB23
62+
D46 = PB21
63+
D47 = PD08
64+
D48 = PD09
65+
D49 = PB04
66+
D50 = PB05
67+
D51 = PD14
68+
D52 = PD13
69+
D53 = PD12
70+
D54 = PD15
71+
D55 = PD11
72+
D56 = PE10
73+
D57 = PE11
74+
D58 = PE00
75+
D59 = PE01
76+
D60 = PE02
77+
D61 = PE03
78+
D62 = PE04
79+
D63 = PE05
80+
)
2281

23-
var pins = []pin{
24-
// {bit, control register, gpio register bank}
25-
0: {16, &nxp.PORTB.PCR16, nxp.GPIOB},
26-
1: {17, &nxp.PORTB.PCR17, nxp.GPIOB},
27-
2: {0, &nxp.PORTD.PCR0, nxp.GPIOD},
28-
3: {12, &nxp.PORTA.PCR12, nxp.GPIOA},
29-
4: {13, &nxp.PORTA.PCR13, nxp.GPIOA},
30-
5: {7, &nxp.PORTD.PCR7, nxp.GPIOD},
31-
6: {4, &nxp.PORTD.PCR4, nxp.GPIOD},
32-
7: {2, &nxp.PORTD.PCR2, nxp.GPIOD},
33-
8: {3, &nxp.PORTD.PCR3, nxp.GPIOD},
34-
9: {3, &nxp.PORTC.PCR3, nxp.GPIOC},
35-
10: {4, &nxp.PORTC.PCR4, nxp.GPIOC},
36-
11: {6, &nxp.PORTC.PCR6, nxp.GPIOC},
37-
12: {7, &nxp.PORTC.PCR7, nxp.GPIOC},
38-
13: {5, &nxp.PORTC.PCR5, nxp.GPIOC},
39-
14: {1, &nxp.PORTD.PCR1, nxp.GPIOD},
40-
15: {0, &nxp.PORTC.PCR0, nxp.GPIOC},
41-
16: {0, &nxp.PORTB.PCR0, nxp.GPIOB},
42-
17: {1, &nxp.PORTB.PCR1, nxp.GPIOB},
43-
18: {3, &nxp.PORTB.PCR3, nxp.GPIOB},
44-
19: {2, &nxp.PORTB.PCR2, nxp.GPIOB},
45-
20: {5, &nxp.PORTD.PCR5, nxp.GPIOD},
46-
21: {6, &nxp.PORTD.PCR6, nxp.GPIOD},
47-
22: {1, &nxp.PORTC.PCR1, nxp.GPIOC},
48-
23: {2, &nxp.PORTC.PCR2, nxp.GPIOC},
49-
24: {26, &nxp.PORTE.PCR26, nxp.GPIOE},
50-
25: {5, &nxp.PORTA.PCR5, nxp.GPIOA},
51-
26: {14, &nxp.PORTA.PCR14, nxp.GPIOA},
52-
27: {15, &nxp.PORTA.PCR15, nxp.GPIOA},
53-
28: {16, &nxp.PORTA.PCR16, nxp.GPIOA},
54-
29: {18, &nxp.PORTB.PCR18, nxp.GPIOB},
55-
30: {19, &nxp.PORTB.PCR19, nxp.GPIOB},
56-
31: {10, &nxp.PORTB.PCR10, nxp.GPIOB},
57-
32: {11, &nxp.PORTB.PCR11, nxp.GPIOB},
58-
33: {24, &nxp.PORTE.PCR24, nxp.GPIOE},
59-
34: {25, &nxp.PORTE.PCR25, nxp.GPIOE},
60-
35: {8, &nxp.PORTC.PCR8, nxp.GPIOC},
61-
36: {9, &nxp.PORTC.PCR9, nxp.GPIOC},
62-
37: {10, &nxp.PORTC.PCR10, nxp.GPIOC},
63-
38: {11, &nxp.PORTC.PCR11, nxp.GPIOC},
64-
39: {17, &nxp.PORTA.PCR17, nxp.GPIOA},
65-
40: {28, &nxp.PORTA.PCR28, nxp.GPIOA},
66-
41: {29, &nxp.PORTA.PCR29, nxp.GPIOA},
67-
42: {26, &nxp.PORTA.PCR26, nxp.GPIOA},
68-
43: {20, &nxp.PORTB.PCR20, nxp.GPIOB},
69-
44: {22, &nxp.PORTB.PCR22, nxp.GPIOB},
70-
45: {23, &nxp.PORTB.PCR23, nxp.GPIOB},
71-
46: {21, &nxp.PORTB.PCR21, nxp.GPIOB},
72-
47: {8, &nxp.PORTD.PCR8, nxp.GPIOD},
73-
48: {9, &nxp.PORTD.PCR9, nxp.GPIOD},
74-
49: {4, &nxp.PORTB.PCR4, nxp.GPIOB},
75-
50: {5, &nxp.PORTB.PCR5, nxp.GPIOB},
76-
51: {14, &nxp.PORTD.PCR14, nxp.GPIOD},
77-
52: {13, &nxp.PORTD.PCR13, nxp.GPIOD},
78-
53: {12, &nxp.PORTD.PCR12, nxp.GPIOD},
79-
54: {15, &nxp.PORTD.PCR15, nxp.GPIOD},
80-
55: {11, &nxp.PORTD.PCR11, nxp.GPIOD},
81-
56: {10, &nxp.PORTE.PCR10, nxp.GPIOE},
82-
57: {11, &nxp.PORTE.PCR11, nxp.GPIOE},
83-
58: {0, &nxp.PORTE.PCR0, nxp.GPIOE},
84-
59: {1, &nxp.PORTE.PCR1, nxp.GPIOE},
85-
60: {2, &nxp.PORTE.PCR2, nxp.GPIOE},
86-
61: {3, &nxp.PORTE.PCR3, nxp.GPIOE},
87-
62: {4, &nxp.PORTE.PCR4, nxp.GPIOE},
88-
63: {5, &nxp.PORTE.PCR5, nxp.GPIOE},
89-
}
82+
var (
83+
TeensyUART1 = &UART0
84+
TeensyUART2 = &UART1
85+
TeensyUART3 = &UART2
86+
TeensyUART4 = &UART3
87+
TeensyUART5 = &UART4
88+
)
9089

91-
//go:inline
92-
func (p Pin) reg() pin { return pins[p] }
90+
const (
91+
defaultUART0RX = D00
92+
defaultUART0TX = D01
93+
defaultUART1RX = D09
94+
defaultUART1TX = D10
95+
defaultUART2RX = D07
96+
defaultUART2TX = D08
97+
defaultUART3RX = D31
98+
defaultUART3TX = D32
99+
defaultUART4RX = D34
100+
defaultUART4TX = D33
101+
)

‎src/machine/machine_nxp.go‎

Lines changed: 0 additions & 33 deletions
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