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aykevldeadprogram
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tools/gen-device-svd: refactor to make the code more declarative
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tools/gen-device-svd.py

Lines changed: 50 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -234,55 +234,73 @@ def parseBitfields(groupName, regName, fieldsEls, bitfieldPrefix=''):
234234
})
235235
return fields
236236

237+
class Register:
238+
def __init__(self, element, baseAddress):
239+
self.element = element
240+
self.baseAddress = baseAddress
241+
242+
def name(self):
243+
return getText(self.element.find('name')).replace('[%s]', '')
244+
245+
def description(self):
246+
return getText(self.element.find('description')).replace('\n', ' ')
247+
248+
def address(self):
249+
offsetEls = self.element.findall('offset')
250+
if not offsetEls:
251+
offsetEls = self.element.findall('addressOffset')
252+
return self.baseAddress + int(getText(offsetEls[0]), 0)
253+
254+
def dim(self):
255+
dimEls = self.element.findall('dim')
256+
if len(dimEls) == 0:
257+
return None
258+
elif len(dimEls) == 1:
259+
return int(getText(dimEls[0]), 0)
260+
else:
261+
raise ValueError('expected at most one <dim> element in %s register' % self.name())
262+
263+
def size(self):
264+
size = 4
265+
elSizes = self.element.findall('size')
266+
if elSizes:
267+
size = int(getText(elSizes[0]), 0) // 8
268+
return size
269+
270+
237271
def parseRegister(groupName, regEl, baseAddress, bitfieldPrefix=''):
238-
regName = getText(regEl.find('name'))
239-
regDescription = getText(regEl.find('description'))
240-
offsetEls = regEl.findall('offset')
241-
if not offsetEls:
242-
offsetEls = regEl.findall('addressOffset')
243-
address = baseAddress + int(getText(offsetEls[0]), 0)
244-
245-
size = 4
246-
elSizes = regEl.findall('size')
247-
if elSizes:
248-
size = int(getText(elSizes[0]), 0) // 8
249-
250-
dimEls = regEl.findall('dim')
272+
reg = Register(regEl, baseAddress)
273+
251274
fieldsEls = regEl.findall('fields')
252275

253-
array = None
254-
if dimEls:
255-
array = int(getText(dimEls[0]), 0)
276+
if reg.dim() is not None:
256277
dimIncrement = int(getText(regEl.find('dimIncrement')), 0)
257-
if "[%s]" in regName:
258-
# just a normal array of registers
259-
regName = regName.replace('[%s]', '')
260-
elif "%s" in regName:
278+
if "%s" in reg.name():
261279
# a "spaced array" of registers, special processing required
262280
# we need to generate a separate register for each "element"
263281
results = []
264-
for i in range(array):
265-
regAddress = address + (i * dimIncrement)
282+
for i in range(reg.dim()):
283+
regAddress = reg.address() + (i * dimIncrement)
266284
results.append({
267-
'name': regName.replace('%s', str(i)),
285+
'name': reg.name().replace('%s', str(i)),
268286
'address': regAddress,
269-
'description': regDescription.replace('\n', ' '),
287+
'description': reg.description(),
270288
'bitfields': [],
271289
'array': None,
272-
'elementsize': size,
290+
'elementsize': reg.size(),
273291
})
274292
# set first result bitfield
275-
shortName = regName.replace('_%s', '').replace('%s', '')
293+
shortName = reg.name().replace('_%s', '').replace('%s', '')
276294
results[0]['bitfields'] = parseBitfields(groupName, shortName, fieldsEls, bitfieldPrefix)
277295
return results
278296

279297
return [{
280-
'name': regName,
281-
'address': address,
282-
'description': regDescription.replace('\n', ' '),
283-
'bitfields': parseBitfields(groupName, regName, fieldsEls, bitfieldPrefix),
284-
'array': array,
285-
'elementsize': size,
298+
'name': reg.name(),
299+
'address': reg.address(),
300+
'description': reg.description(),
301+
'bitfields': parseBitfields(groupName, reg.name(), fieldsEls, bitfieldPrefix),
302+
'array': reg.dim(),
303+
'elementsize': reg.size(),
286304
}]
287305

288306
def writeGo(outdir, device):

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