@@ -234,55 +234,73 @@ def parseBitfields(groupName, regName, fieldsEls, bitfieldPrefix=''):
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})
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return fields
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+ class Register :
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+ def __init__ (self , element , baseAddress ):
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+ self .element = element
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+ self .baseAddress = baseAddress
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+
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+ def name (self ):
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+ return getText (self .element .find ('name' )).replace ('[%s]' , '' )
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+
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+ def description (self ):
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+ return getText (self .element .find ('description' )).replace ('\n ' , ' ' )
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+
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+ def address (self ):
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+ offsetEls = self .element .findall ('offset' )
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+ if not offsetEls :
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+ offsetEls = self .element .findall ('addressOffset' )
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+ return self .baseAddress + int (getText (offsetEls [0 ]), 0 )
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+
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+ def dim (self ):
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+ dimEls = self .element .findall ('dim' )
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+ if len (dimEls ) == 0 :
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+ return None
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+ elif len (dimEls ) == 1 :
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+ return int (getText (dimEls [0 ]), 0 )
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+ else :
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+ raise ValueError ('expected at most one <dim> element in %s register' % self .name ())
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+
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+ def size (self ):
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+ size = 4
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+ elSizes = self .element .findall ('size' )
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+ if elSizes :
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+ size = int (getText (elSizes [0 ]), 0 ) // 8
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+ return size
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+
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+
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def parseRegister (groupName , regEl , baseAddress , bitfieldPrefix = '' ):
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- regName = getText (regEl .find ('name' ))
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- regDescription = getText (regEl .find ('description' ))
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- offsetEls = regEl .findall ('offset' )
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- if not offsetEls :
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- offsetEls = regEl .findall ('addressOffset' )
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- address = baseAddress + int (getText (offsetEls [0 ]), 0 )
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-
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- size = 4
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- elSizes = regEl .findall ('size' )
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- if elSizes :
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- size = int (getText (elSizes [0 ]), 0 ) // 8
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-
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- dimEls = regEl .findall ('dim' )
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+ reg = Register (regEl , baseAddress )
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+
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fieldsEls = regEl .findall ('fields' )
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- array = None
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- if dimEls :
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- array = int (getText (dimEls [0 ]), 0 )
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+ if reg .dim () is not None :
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dimIncrement = int (getText (regEl .find ('dimIncrement' )), 0 )
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- if "[%s]" in regName :
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- # just a normal array of registers
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- regName = regName .replace ('[%s]' , '' )
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- elif "%s" in regName :
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+ if "%s" in reg .name ():
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# a "spaced array" of registers, special processing required
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# we need to generate a separate register for each "element"
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results = []
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- for i in range (array ):
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- regAddress = address + (i * dimIncrement )
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+ for i in range (reg . dim () ):
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+ regAddress = reg . address () + (i * dimIncrement )
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results .append ({
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- 'name' : regName .replace ('%s' , str (i )),
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+ 'name' : reg . name () .replace ('%s' , str (i )),
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'address' : regAddress ,
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- 'description' : regDescription . replace ( ' \n ' , ' ' ),
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+ 'description' : reg . description ( ),
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'bitfields' : [],
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'array' : None ,
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- 'elementsize' : size ,
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+ 'elementsize' : reg . size () ,
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})
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# set first result bitfield
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- shortName = regName .replace ('_%s' , '' ).replace ('%s' , '' )
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+ shortName = reg . name () .replace ('_%s' , '' ).replace ('%s' , '' )
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results [0 ]['bitfields' ] = parseBitfields (groupName , shortName , fieldsEls , bitfieldPrefix )
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return results
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return [{
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- 'name' : regName ,
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- 'address' : address ,
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- 'description' : regDescription . replace ( ' \n ' , ' ' ),
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- 'bitfields' : parseBitfields (groupName , regName , fieldsEls , bitfieldPrefix ),
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- 'array' : array ,
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- 'elementsize' : size ,
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+ 'name' : reg . name () ,
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+ 'address' : reg . address () ,
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+ 'description' : reg . description ( ),
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+ 'bitfields' : parseBitfields (groupName , reg . name () , fieldsEls , bitfieldPrefix ),
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+ 'array' : reg . dim () ,
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+ 'elementsize' : reg . size () ,
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}]
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def writeGo (outdir , device ):
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