Schematic revisions 2022/10/8

[alastairpatrick]

A couple of things I noticed. Firstly, one of RN3C or RN4C should pull down ICE_FLASH_IO2 rather than ICE_FLASH_IO3

Secondly, rise time for FPGA SRAM /CS could be several RP2040 or FPGA cycles. Back of envelope RC time constant is about 100ns. The PSRAM must see high on /CS to terminate commands correctly so RP2040 or FPGA may need to delay subsequent commands to allow time for correct termination. For comparison, datasheet says "CE# hold time from CLK rising edge" is 3ns.

[vr2045]

Yes, my mistake doing things in a hurry. Will fix.
True, there's a timing penalty for this sort of a transistor solution. Trying to minimize supply chain issues by going with a transistor solution rather than a dedicated gate. Besides, it's also low cost.