Intercommunication between the RP2040 and FPGA

[josuah]

Given they are two component that are about to interact a lot on the same board, this thread aims to collect options for possible interactions: bus protocols, debug UART, hardened or gateware SPI...

[josuah]

Quoting @jrwagz
Using an external RAM chip with DMA on the RP2040 to send/receive data that the FPGA reads:

[josuah]

As suggested on the chat:

On the topic of how the RP2040/FPGA can communicate back and forth, there are obviously many options here. I'll present an example architecture that scales well, and provides lots of flexibility. Consider a mailbox/doorbell approach as follows. The FPGA has some piece of RAM that the RP2040 has direct memory access to (not hard to create a SPI/UART/I2C to memory interface in RTL which performs reads/writes to the RAM based on data from the SPI/UART/I2C interface). Then there is a special register on the FPGA side that allows the RP2040 to tell the FPGA that it's done writing to the mailbox and that it should interpret the contents. After the FPGA is done processing the command(s) in the mailbox, it writes it's response into the mailbox and then asserts an interrupt back to the RP2040 to tell it that it's results are ready. The RP2040 then reads the mailbox to see the results of it's request. You could obviously optimize this even further with more complicated bi-directional data mechanisms, but this architecture even scales all the way down to the FPGA being simply an I2C target that the RP2040 has access to.

[josuah]

Think of in the simplest case, the FPGA implements an I2C target, which translates I2C transactions into read/write transactions to the RAM in question. Perhaps this is to a RAM that a RISCV processor on the FPGA also has access to, or perhaps just to a RAM that RTL on the FPGA reads/writes to. But the key is just to convert transactions on the SPI/UART/I2C/etc interface into memory read/write transactions inside the FPGA, preferably in RTL, so that any processor on the FPGA doesn't have to be involved

[josuah]

Using the hardened SPI interface, otherwise used to program the FPGA flash.

[josuah]

This interface is not in use after we flash the FPGA, and connected to the iCE40 hardened core, which means no SPI module to implement on the FPGA, saving resources for the user RTL design.

[josuah]

It is planned that the RP2040 can communicate using DMA to this hardened core.

[josuah]

External 8-bit bus + control signals

[josuah]

@z80 suggested exposing an 8-bit interconnect through an high-throughput 8-bit bus, in the same style as the 8051 external bus.

[josuah]

I think these were the signals evoked to fit in:

• A/D 0-7 - Address or Data
• ALE - Address Latch Enable, so that the A/D port gets latched into the address register for the transaction
• /RD, /WR - On any pulse the data gets read/written to/from the bus, until a response comes back
• /IRQ - An independent pin used for event notifications from the FPGA to the MCU