Confusion regarding upper right ice-pico pmod

[MrJake222]

According to this the "Upper right PMOD" pins are connected to the SPI bus. However the schematic shows that the PMOD and SPI bus get their own pins:

According to SPI Pinouts docs here, for example pin 20 would be shorted with pin 12?

Also this would break second UART forwarding and be really limiting in ice-pico communications when the flash is in use after the bitstream is read?

[josuah]

I notice that I never came back to answer this. Sorry about that.

Yes you are right, there are some inconsistencies. For instance, ICE_FLASH_IO2 that you are pointing at is not brought to a Pmod:

These must have been debug signals added by the author, exporting them to FPGA signals through the RTL design rather than representing the interconnections at the PCB level.

This will need some verification.

Thanks for pointing it!