Board/Rev0.2/pico-ice.kicad_sch - 2022/06/22

[josuah]

https://github.com/tinyvision-ai-inc/pico-ice/blob/main/Board/Rev0/For%20Review/pico-ice_r0.2.pdf

[josuah]

RP2040-pinout:
This time, I could not find anything to consider about the pinout. Looking good!

[vr2045]

Cool! This is good progress, thanks to you and the rest of the community for the feedback!

[josuah]

TODO: Unify parts to minimize BoM

[josuah]

The resistors are 10kOhm for most, but there are a few 1k (around the crystal and around the flash button, a pulldown resistor it seems).

[vr2045]

Yes, this is something I want to comb through again just to be sure. I barely tolerate ordering and managing parts :)

[josuah]

                  J5 (1)  Connector:Conn_ARM_JTAG_SWD_10  Conn_ARM_JTAG_SWD_10
                  J9 (1)  Connector_Generic:Conn_01x02  BOOT_SEL
                  J2 (1)  Connector_Generic:Conn_02x06_Row_Letter_First  SPARE
                  J3 (1)  Connector_Generic:Conn_02x06_Row_Letter_First  PMOD_PICO
                  J4 (1)  Connector_Generic:Conn_02x06_Row_Letter_First  Dual PMOD A
                  J6 (1)  Connector_Generic:Conn_02x06_Row_Letter_First  Single PMOD
                  J7 (1)  Connector_Generic:Conn_02x06_Row_Letter_First  SPARES
                  J8 (1)  Connector_Generic:Conn_02x06_Row_Letter_First  Dual PMOD B
              C1, C2 (2)  Device:C  27p
             C6, C11 (2)  Device:C  1u
                  Y1 (1)  Device:Crystal  ABLS-12.000MHZ-B4-T
              R1, R2 (2)  Device:R  1k
          R4, R5, R6 (3)  Device:R  27
      H1, H2, H3, H4 (4)  Mechanical:MountingHole  MountingHole
                  U1 (1)  Regulator_Linear:NCP1117-3.3_SOT223  NCP1117-3.3_SOT223
                 SW1 (1)  Switch:SW_Push  ~{RESET}
                 SW2 (1)  Switch:SW_Push  SW_Push
                  U4 (1)  UPduino_v3.0:AP2127K-1.2  AP2127K-1.2
                 TP1 (1)  UPduino_v3.0:Connector_TestPoint  TestPoint
                  J1 (1)  UPduino_v3.0:Connector_USB_B_Micro  Connector_USB_B_Micro
                  D3 (1)  UPduino_v3.0:Device_LED_ALT  LTST-C191KGKT
              D2, D4 (2)  UPduino_v3.0:Device_LED_ARGB  CLMVC-FKA-CLBDGL7LBB79353
                 R11 (1)  UPduino_v3.0:Device_R  100
  R14, R18, R19, R20 (4)  UPduino_v3.0:Device_R  2.2K
                PTC1 (1)  UPduino_v3.0:Device_R  MF-FSMF035X-2
       R10, SJ4, SJ5 (3)  UPduino_v3.0:Device_R  SHORT
                 SJ6 (1)  UPduino_v3.0:Device_R  OPEN
                  D1 (1)  UPduino_v3.0:Diode_1N4148W  1N4148WT-7
                  U6 (1)  UPduino_v3.0:ICE40UP5K-SG48ITR-FPGA_Lattice  ICE40UP5K-SG48ITR
              U2, U8 (2)  UPduino_v3.0:W25Q32JVSS-Memory_Flash  W25Q32JVSSIM
                  U5 (1)  UPduino_v3.0:W25Q32JVSS-Memory_Flash  APS6404L-3SQN
                  U3 (1)  pico-ice_minimal:MCU_RaspberryPi_RP2040_RP2040  RP2040

[josuah]

This is a quick awk script sorting and displaying all components with less than 5 (4 or less) instances through the board.

P.S.: for reference: csv2tsv <Board/Rev0/pico-ice.csv | sort -k 5 -t ' ' | awk -F '[\t]' '$2 > 0 && $2 < 5 { printf("%20s (%s) %s %s\n", $3, $2, $5, $4) }'

[josuah]

C1, C2               (2)  Device:C  27p
C6, C11              (2)  Device:C  1u
D1                   (1)  UPduino_v3.0:Diode_1N4148W  1N4148WT-7
D2, D4               (2)  UPduino_v3.0:Device_LED_ARGB  CLMVC-FKA-CLBDGL7LBB79353
D3                   (1)  UPduino_v3.0:Device_LED_ALT  LTST-C191KGKT
H1, H2, H3, H4       (4)  Mechanical:MountingHole  MountingHole
J1                   (1)  UPduino_v3.0:Connector_USB_B_Micro  Connector_USB_B_Micro
J2                   (1)  Connector_Generic:Conn_02x06_Row_Letter_First  SPARE
J3                   (1)  Connector_Generic:Conn_02x06_Row_Letter_First  PMOD_PICO
J4                   (1)  Connector_Generic:Conn_02x06_Row_Letter_First  Dual PMOD A
J5                   (1)  Connector:Conn_ARM_JTAG_SWD_10  Conn_ARM_JTAG_SWD_10
J6                   (1)  Connector_Generic:Conn_02x06_Row_Letter_First  Single PMOD
J7                   (1)  Connector_Generic:Conn_02x06_Row_Letter_First  SPARES
J8                   (1)  Connector_Generic:Conn_02x06_Row_Letter_First  Dual PMOD B
J9                   (1)  Connector_Generic:Conn_01x02  BOOT_SEL
PTC1                 (1)  UPduino_v3.0:Device_R  MF-FSMF035X-2
R1, R2               (2)  Device:R  1k
R10, SJ4, SJ5        (3)  UPduino_v3.0:Device_R  SHORT
R11                  (1)  UPduino_v3.0:Device_R  100
R14, R18, R19, R20   (4)  UPduino_v3.0:Device_R  2.2K
R4, R5, R6           (3)  Device:R  27
SJ6                  (1)  UPduino_v3.0:Device_R  OPEN
SW1                  (1)  Switch:SW_Push  ~{RESET}
SW2                  (1)  Switch:SW_Push  SW_Push
TP1                  (1)  UPduino_v3.0:Connector_TestPoint  TestPoint
U1                   (1)  Regulator_Linear:NCP1117-3.3_SOT223  NCP1117-3.3_SOT223
U2, U8               (2)  UPduino_v3.0:W25Q32JVSS-Memory_Flash  W25Q32JVSSIM
U3                   (1)  pico-ice_minimal:MCU_RaspberryPi_RP2040_RP2040  RP2040
U4                   (1)  UPduino_v3.0:AP2127K-1.2  AP2127K-1.2
U5                   (1)  UPduino_v3.0:W25Q32JVSS-Memory_Flash  APS6404L-3SQN
U6                   (1)  UPduino_v3.0:ICE40UP5K-SG48ITR-FPGA_Lattice  ICE40UP5K-SG48ITR
Y1                   (1)  Device:Crystal  ABLS-12.000MHZ-B4-T

The same, but sorted per instance name, to have these R[0-9] line-up...

[josuah]

(from #pico-ice by ggrummer)
Lattice-IDE:
Can the FPGA be programmed using Lattice Radiant?

[josuah]

I believe once a bitstream is generated by Lattice, or any other tool, then uploading it with some other program would work fine.

But if Lattice expects to find an FTDI and nothing else, then it would not program the flash directly from Radiant, as it is getting really hard to find FTDI, reason why pico-board is being worked on.

[josuah]

Regardless of the upload method, because a microcontroller (RP2040) is in charge of programming the FPGA flash, it gives somewhat more flexibility, and eventually make it behave in the way Radiant expects. So maybe something can be worked out.

[vr2045]

The Radiant programmer does expect an ftdi part unfortunately so won't work out. However as @josuah mentioned, this board should be able to support a drag-drop or a scripted way to move the bitfile from any OS to the flash on the board (still to be developed!).

[ggrummer]

As long as there's a way to get the .bin file (produced by Radiant) into the FPGA, all is well.

[josuah]

(from #pico-ice by ggrummer)
only-1-testpoint:
On the schematic, I see only 1 test point (on +1V2). Why only that net and no others?

[vr2045]

Haven't yet done a DFM pass on the board, that's a left over from the original upduino's schematic for now.
Are there any specific nets you want to see on the headers or else on test points?

[ggrummer]

I don't have any specific nets in mind. I don't see the need for test points when one can probe a net on a passive component.

[ggrummer]

From a signal integrity point of view, it would be ideal to have one Clock GPOUTx drive the clock to the FPGA and a second to dive a clock off board.

[vr2045]

Good idea! Could this allow the external device to have a somewhat programmable clock too and not necessarily be the same as the FPGA clock?
I took up the space of 1 ADC GPIO and moved things around in v0.3 so the CLOCK GPOUT is an independent pin to a header.

[josuah]

(from #pico-ice by ggrummer)
clock-jitter:
The ICE_CLK worries me. On the UPduino_3.0, the clock is buffered (via two 125 buffers) to different places. On pico-ice it isn’t, net ICE_35_G0 goes to the FPGA and off board. This could lead to signal integrity issues. Additionally, this clock will have the added jitter caused by sourcing it from a GPIO (on the RP2040). Buffering it (like on the UPduino_3.0) is the best solution, but if that’s no longer on the table, add some 0-ohm resistors that can be hacked off to direct the signal to 1 load.

[josuah]

The feature from the RP2040 here is exporting the clock signal, after it eventually went through RP2040 PLL.
Not sure if it can be a bit better from plain GPIO.

From the RP2040 datasheet:

CLOCK GPOUTx General purpose clock outputs. Can drive a number of internal clocks (including PLL outputs) onto GPIOs, with optional integer divide.

[vr2045]

Yes, running the clock from the RP output will add some jitter as compared to getting this from the xtal. The PLL minimizes this.
I decided to do this as it gives the RP control of clock to the fpga which I think is quite a significant hackable feature. Eg can gate, dynamically change clock etc.

[ggrummer]

Since the datasheet doesn't have many actual timing numbers, one is left to assume a dedicated clock GPIO would preform better then a plain GPIO.
I like the "significant hackable feature".

[josuah]

The use-case listed is debugging and clock external devices:

Clock output to GPIO. Can be used to clock external devices or debug on chip clocks with a logic analyser or oscilloscope.

So hopefully RPi did a good job at preserving signal integrity on their clock here.