diff --git a/boards/st/stm32h7s78_dk/board.cmake b/boards/st/stm32h7s78_dk/board.cmake
index 79bb6fcc70bef..2039c4fe5d83d 100644
--- a/boards/st/stm32h7s78_dk/board.cmake
+++ b/boards/st/stm32h7s78_dk/board.cmake
@@ -2,6 +2,8 @@
 
 # keep first
 board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
+board_runner_args(stm32cubeprogrammer "--extload=MX66UW1G45G_STM32H7S78-DK.stldr")
+
 board_runner_args(openocd --target-handle=_CHIPNAME.cpu0)
 
 # keep first
diff --git a/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts b/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts
index 5cfbbb449b85a..074c37056426e 100644
--- a/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts
+++ b/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts
@@ -9,6 +9,8 @@
 #include <st/h7/stm32h7s7l8hx-pinctrl.dtsi>
 #include "arduino_r3_connector.dtsi"
 #include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <zephyr/dt-bindings/flash_controller/xspi.h>
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
 
 / {
 	model = "STMicroelectronics STM32H7S78 DISCOVERY KIT board";
@@ -18,7 +20,9 @@
 		zephyr,console = &uart4;
 		zephyr,shell-uart = &uart4;
 		zephyr,flash = &flash0;
+		zephyr,flash-controller = &mx66uw1g45g;
 		zephyr,sram = &sram0;
+		zephyr,code-partition = &slot0_partition;
 	};
 
 	leds {
@@ -60,6 +64,11 @@
 	};
 };
 
+&ext_memory {
+	/* ATTR_MPU_EXTMEM is causing MPU FAULT */
+	zephyr,memory-attr = <DT_MEM_ARM_MPU_IO>;
+};
+
 &clk_hsi48 {
 	status = "okay";
 };
@@ -185,6 +194,66 @@
 	status = "okay";
 };
 
+&xspi2 {
+	pinctrl-0 = <&xspim_p2_clk_pn6 &xspim_p2_ncs1_pn1
+		     &xspim_p2_io0_pn2 &xspim_p2_io1_pn3
+		     &xspim_p2_io2_pn4 &xspim_p2_io3_pn5
+		     &xspim_p2_io4_pn8 &xspim_p2_io5_pn9
+		     &xspim_p2_io6_pn10 &xspim_p2_io7_pn11
+		     &xspim_p2_dqs0_pn0>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	mx66uw1g45g: xspi-nor-flash@70000000 {
+		compatible = "st,stm32-xspi-nor";
+		reg = <0x70000000 DT_SIZE_M(128)>; /* 1 Gbits */
+		ospi-max-frequency = <DT_FREQ_M(100)>;
+		spi-bus-width = <XSPI_OCTO_MODE>;
+		data-rate = <XSPI_DTR_TRANSFER>;
+		four-byte-opcodes;
+		status = "okay";
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			slot0_partition: partition@0 {
+				label = "image-0";
+				reg = <0x00000000 DT_SIZE_M(1)>;
+			};
+
+			slot1_partition: partition@100000 {
+				label = "image-1";
+				reg = <0x00100000 DT_SIZE_M(1)>;
+			};
+
+			scratch_partition: partition@200000 {
+				label = "image-scratch";
+				reg = <0x00200000 DT_SIZE_M(1)>;
+			};
+
+			storage_partition: partition@300000 {
+				label = "storage";
+				reg = <0x00300000 DT_SIZE_M(125)>;
+			};
+		};
+	};
+};
+
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0 DT_SIZE_K(64)>;
+		};
+	};
+};
+
 usb2: &usbotg_fs {
 	pinctrl-0 = <&usb_otg_fs_dm_pm12 &usb_otg_fs_dp_pm11>;
 	pinctrl-names = "default";
diff --git a/drivers/flash/flash_stm32_xspi.c b/drivers/flash/flash_stm32_xspi.c
index 0cb785c7df5a8..b28d353b3b5e3 100644
--- a/drivers/flash/flash_stm32_xspi.c
+++ b/drivers/flash/flash_stm32_xspi.c
@@ -2163,6 +2163,7 @@ static int flash_stm32_xspi_init(const struct device *dev)
 
 #endif /* XSPIM */
 
+#if defined(XSPI_DCR1_DLYBYP)
 #if defined(DLYB_XSPI1) || defined(DLYB_XSPI2) || defined(DLYB_OCTOSPI1) || defined(DLYB_OCTOSPI2)
 	/* XSPI delay block init Function */
 	HAL_XSPI_DLYB_CfgTypeDef xspi_delay_block_cfg = {0};
@@ -2178,6 +2179,7 @@ static int flash_stm32_xspi_init(const struct device *dev)
 
 	LOG_DBG("Delay Block Init");
 #endif /* DLYB_ */
+#endif /* XSPI_DCR1_DLYBYP */
 
 #if STM32_XSPI_USE_DMA
 	/* Configure and enable the DMA channels after XSPI config */
diff --git a/dts/arm/st/h7rs/stm32h7rs.dtsi b/dts/arm/st/h7rs/stm32h7rs.dtsi
index e41e465c7ebfa..d9b42c918c8b9 100644
--- a/dts/arm/st/h7rs/stm32h7rs.dtsi
+++ b/dts/arm/st/h7rs/stm32h7rs.dtsi
@@ -428,6 +428,28 @@
 			status = "disabled";
 		};
 
+		xspi1: spi@52005000 {
+			compatible = "st,stm32-xspi";
+			reg = <0x52005000 0x1000>;
+			interrupts = <105 0>;
+			clock-names = "bus";
+			clocks = <&rcc STM32_CLOCK(AHB5, 5U)>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		xspi2: spi@5200a000 {
+			compatible = "st,stm32-xspi";
+			reg = <0x5200a000 0x1000>;
+			interrupts = <106 0>;
+			clock-names = "bus";
+			clocks = <&rcc STM32_CLOCK(AHB5, 12U)>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		spi1: spi@42003000 {
 			compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
 			#address-cells = <1>;