diff --git a/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts b/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts
index 792b48ccd8be4..b786420691a14 100644
--- a/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts
+++ b/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts
@@ -185,6 +185,12 @@
 	status = "okay";
 };
 
+usb1: &usbotg_hs {
+	pinctrl-0 = <&usb_otg_hs_dm_pm5 &usb_otg_hs_dp_pm6>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 usb2: &usbotg_fs {
 	pinctrl-0 = <&usb_otg_fs_dm_pm12 &usb_otg_fs_dp_pm11>;
 	pinctrl-names = "default";
diff --git a/dts/arm/st/h7rs/stm32h7rs.dtsi b/dts/arm/st/h7rs/stm32h7rs.dtsi
index e41e465c7ebfa..ac0453b2d3df9 100644
--- a/dts/arm/st/h7rs/stm32h7rs.dtsi
+++ b/dts/arm/st/h7rs/stm32h7rs.dtsi
@@ -790,6 +790,27 @@
 				 <&rcc STM32_SRC_HSI48 OTGFS_SEL(0)>;
 			status = "disabled";
 		};
+
+		usbotg_hs: usb@40040000 {
+			compatible = "st,stm32-otghs";
+			reg = <0x40040000 0x40000>;
+			interrupts = <91 0>;
+			interrupt-names = "otghs";
+			num-bidir-endpoints = <9>;
+			ram-size = <DT_SIZE_K(4)>;
+			maximum-speed = "high-speed";
+			phys = <&usbphyc1>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 25U)>;
+			status = "disabled";
+		};
+	};
+
+	usbphyc1: usbphyc@4000ec00 {
+		compatible = "st,stm32-usbphyc";
+		reg = <0x4000ec00 0x400>;
+		clocks = <&rcc STM32_CLOCK(AHB1, 26U)>,
+			 <&rcc STM32_SRC_HSE USBPHYC_SEL(0)>;
+		#phy-cells = <0>;
 	};
 
 	otgfs_phy: otgfs_phy {
diff --git a/include/zephyr/dt-bindings/clock/stm32h7rs_clock.h b/include/zephyr/dt-bindings/clock/stm32h7rs_clock.h
index d7943dbe73bca..222494ab43369 100644
--- a/include/zephyr/dt-bindings/clock/stm32h7rs_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32h7rs_clock.h
@@ -75,6 +75,7 @@
 #define SDMMC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 2, D1CCIPR_REG)
 #define XSPI1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 4, D1CCIPR_REG)
 #define XSPI2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 6, D1CCIPR_REG)
+#define USBPHYC_SEL(val)	STM32_DT_CLOCK_SELECT((val), 3, 12, D1CCIPR_REG)
 #define OTGFS_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 14, D1CCIPR_REG)
 #define ADC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 24, D1CCIPR_REG)
 #define CKPER_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 28, D1CCIPR_REG)