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1 parent 7e3ef84 commit 28e9670Copy full SHA for 28e9670
cmd/generate/main.go
@@ -54,8 +54,8 @@ func main() {
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svFile = verilog.NewVerilogFile("snippet.sv")
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module := svFile.CreateModule("snippet")
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module.Ports = []*verilog.Port{
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- {Name: "clk", Direction: verilog.INPUT},
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- {Name: "reset", Direction: verilog.INPUT},
+ {Name: "clk", Direction: verilog.INPUT, Type: verilog.WIRE},
+ {Name: "reset", Direction: verilog.INPUT, Type: verilog.WIRE},
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}
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var ginv float32
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