Random questions

[toby-bro]

Is it normal to support a fork in an always_comb

[toby-bro]

Can i have a unique and a priority on the same case ?

[toby-bro]

Can i have a unique and a priority on the same case ?

Solved in 05c651d

[toby-bro]

Is this a bug
If I ask yosys to prep this module with a conflicting driver I get this output

module simple_sub (
    input logic [7:0] a,
    input logic [7:0] b,
    output logic [7:0] a_out,
    output logic [7:0] b_out,
    output logic [7:0] diff
);
    wire [7:0] conflict_wire;
    assign a_out = a;
    assign b_out = b;
    assign conflict_wire = b;
    assign conflict_wire = a;
    assign diff = a - b;
endmodule

yosys transforms it into

/* Generated by Yosys 0.54 (git sha1 db72ec3bd, g++ 12.2.0-14+deb12u1 -fPIC -O3) */

(* top =  1  *)
(* src = "../simple_sub.sv:1.1-14.10" *)
module simple_sub(a, b, a_out, b_out, diff);
  (* src = "../simple_sub.sv:2.23-2.24" *)
  input [7:0] a;
  wire [7:0] a;
  (* src = "../simple_sub.sv:4.24-4.29" *)
  output [7:0] a_out;
  wire [7:0] a_out;
  (* src = "../simple_sub.sv:3.23-3.24" *)
  input [7:0] b;
  wire [7:0] b;
  (* src = "../simple_sub.sv:5.24-5.29" *)
  output [7:0] b_out;
  wire [7:0] b_out;
  (* src = "../simple_sub.sv:8.16-8.29" *)
  wire [7:0] conflict_wire;
  (* src = "../simple_sub.sv:6.24-6.28" *)
  output [7:0] diff;
  wire [7:0] diff;
  assign diff = a - (* src = "../simple_sub.sv:13.19-13.24" *) a;
  assign a_out = a;
  assign b = a;
  assign b_out = a;
  assign conflict_wire = a;
endmodule