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chipscope.cdc
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65 lines (65 loc) · 2.72 KB
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#ChipScope Core Inserter Project File Version 3.0
#Thu Jun 16 14:57:35 EDT 2022
Project.device.designInputFile=/media/dmishins/1AD0BEB7D0BE9909/Users/Daniel/Desktop/Research/DAPHNE/FEB/FPGA/mu2e/mu2e-daq-firmware-crv/ROC/FPGA2/Controller_FPGA2_cs.ngc
Project.device.designOutputFile=/media/dmishins/1AD0BEB7D0BE9909/Users/Daniel/Desktop/Research/DAPHNE/FEB/FPGA/mu2e/mu2e-daq-firmware-crv/ROC/FPGA2/Controller_FPGA2_cs.ngc
Project.device.deviceFamily=18
Project.device.enableRPMs=true
Project.device.outputDirectory=/media/dmishins/1AD0BEB7D0BE9909/Users/Daniel/Desktop/Research/DAPHNE/FEB/FPGA/mu2e/mu2e-daq-firmware-crv/ROC/FPGA2/_ngo
Project.device.useSRL16=true
Project.filter.dimension=14
Project.filter<0>=
Project.filter<10>=DDR_Read_Seq
Project.filter<11>=DDRWRT_EN
Project.filter<12>=DDRRd_EN
Project.filter<13>=DDRRd
Project.filter<1>=DDR_REad_SEQ
Project.filter<2>=sysclk
Project.filter<3>=waitcount
Project.filter<4>=ddrwrt_en
Project.filter<5>=TxBlkCount[0]
Project.filter<6>=TxBlkCount
Project.filter<7>=AddrBuff_empty
Project.filter<8>=DDRRd_En
Project.filter<9>=ddr
Project.icon.boundaryScanChain=1
Project.icon.enableExtTriggerIn=false
Project.icon.enableExtTriggerOut=false
Project.icon.triggerInPinName=
Project.icon.triggerOutPinName=
Project.unit.dimension=1
Project.unit<0>.clockChannel=SysClk
Project.unit<0>.clockEdge=Rising
Project.unit<0>.dataChannel<0>=DDRRd_en
Project.unit<0>.dataChannel<1>=AddrBuff_empty
Project.unit<0>.dataChannel<2>=TxBlkCount<0>
Project.unit<0>.dataChannel<3>=TxBlkCount<1>
Project.unit<0>.dataChannel<4>=TxBlkCount<2>
Project.unit<0>.dataChannel<5>=DDRWrt_En
Project.unit<0>.dataChannel<6>=SysClk
Project.unit<0>.dataChannel<7>=SysClk
Project.unit<0>.dataDepth=1024
Project.unit<0>.dataEqualsTrigger=true
Project.unit<0>.dataPortWidth=8
Project.unit<0>.enableGaps=false
Project.unit<0>.enableStorageQualification=true
Project.unit<0>.enableTimestamps=false
Project.unit<0>.timestampDepth=0
Project.unit<0>.timestampWidth=0
Project.unit<0>.triggerChannel<0><0>=DDRRd_en
Project.unit<0>.triggerChannel<0><1>=AddrBuff_empty
Project.unit<0>.triggerChannel<0><2>=TxBlkCount<0>
Project.unit<0>.triggerChannel<0><3>=TxBlkCount<1>
Project.unit<0>.triggerChannel<0><4>=TxBlkCount<2>
Project.unit<0>.triggerChannel<0><5>=DDRWrt_En
Project.unit<0>.triggerChannel<0><6>=DDR_Read_Seq_FSM_FFd1
Project.unit<0>.triggerChannel<0><7>=DDR_Read_Seq_FSM_FFd2
Project.unit<0>.triggerConditionCountWidth=0
Project.unit<0>.triggerMatchCount<0>=1
Project.unit<0>.triggerMatchCountWidth<0><0>=0
Project.unit<0>.triggerMatchType<0><0>=1
Project.unit<0>.triggerPortCount=1
Project.unit<0>.triggerPortIsData<0>=true
Project.unit<0>.triggerPortWidth<0>=8
Project.unit<0>.triggerSequencerLevels=16
Project.unit<0>.triggerSequencerType=1
Project.unit<0>.type=ilapro