Revert "[X86] Fold (add X, (srl Y, 7)) -> (sub X, (ashr Y, 7)) on vXi8 vectors" (llvm#143303)

Reverts llvm#143106 as this is causing infinite loops in
llvm#143238

Author: RKSimon

llvm/lib/Target/X86/X86ISelLowering.cpp

@@ -58110,14 +58110,13 @@ static SDValue combineAdd(SDNode *N, SelectionDAG &DAG,
     }
   }
 
+  // If vectors of i1 are legal, turn (add (zext (vXi1 X)), Y) into
+  // (sub Y, (sext (vXi1 X))).
+  // FIXME: We have the (sub Y, (zext (vXi1 X))) -> (add (sext (vXi1 X)), Y) in
+  // generic DAG combine without a legal type check, but adding this there
+  // caused regressions.
   if (VT.isVector()) {
     SDValue X, Y;
-
-    // If vectors of i1 are legal, turn (add (zext (vXi1 X)), Y) into
-    // (sub Y, (sext (vXi1 X))).
-    // FIXME: We have the (sub Y, (zext (vXi1 X))) -> (add (sext (vXi1 X)), Y)
-    // in generic DAG combine without a legal type check, but adding this there
-    // caused regressions.
     EVT BoolVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
                                   VT.getVectorElementCount());
     if (DAG.getTargetLoweringInfo().isTypeLegal(BoolVT) &&
@@ -58126,15 +58125,6 @@ static SDValue combineAdd(SDNode *N, SelectionDAG &DAG,
       SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, X);
       return DAG.getNode(ISD::SUB, DL, VT, Y, SExt);
     }
-
-    // Fold (add X, (srl Y, 7)) -> (sub X, (ashr Y, 7)) to undo instcombine
-    // canonicalisation as we don't have good vXi8 shifts.
-    if (VT.getScalarType() == MVT::i8 &&
-        sd_match(N, m_Add(m_Value(X), m_Srl(m_Value(Y), m_SpecificInt(7))))) {
-      SDValue AShr = DAG.getNode(ISD::SRA, DL, VT, Y,
-                                 DAG.getShiftAmountConstant(7, VT, DL));
-      return DAG.getNode(ISD::SUB, DL, VT, X, AShr);
-    }
   }
 
   // Peephole for 512-bit VPDPBSSD on non-VLX targets.