@@ -8128,24 +8128,6 @@ static SDValue visitORCommutative(SelectionDAG &DAG, SDValue N0, SDValue N1,
81288128 return SDValue();
81298129}
81308130
8131- static SDValue foldMaskedMergeImpl(SDValue AndL0, SDValue AndR0, SDValue AndL1,
8132- SDValue AndR1, const SDLoc &DL,
8133- SelectionDAG &DAG) {
8134- if (!isBitwiseNot(AndL0, true) || !AndL0->hasOneUse())
8135- return SDValue();
8136- SDValue NotOp = AndL0->getOperand(0);
8137- if (NotOp == AndR1)
8138- std::swap(AndR1, AndL1);
8139- if (NotOp != AndL1)
8140- return SDValue();
8141-
8142- EVT VT = AndL1.getValueType();
8143- SDValue Xor0 = DAG.getNode(ISD::XOR, DL, VT, AndR1, AndR0);
8144- SDValue And = DAG.getNode(ISD::AND, DL, VT, Xor0, NotOp);
8145- SDValue Xor1 = DAG.getNode(ISD::XOR, DL, VT, And, AndR0);
8146- return Xor1;
8147- }
8148-
81498131/// Fold "masked merge" expressions like `(m & x) | (~m & y)` into the
81508132/// equivalent `((x ^ y) & m) ^ y)` pattern.
81518133/// This is typically a better representation for targets without a fused
@@ -8155,29 +8137,20 @@ static SDValue foldMaskedMerge(SDNode *Node, SelectionDAG &DAG,
81558137 // Note that masked-merge variants using XOR or ADD expressions are
81568138 // normalized to OR by InstCombine so we only check for OR.
81578139 assert(Node->getOpcode() == ISD::OR && "Must be called with ISD::OR node");
8158- SDValue N0 = Node->getOperand(0);
8159- if (N0->getOpcode() != ISD::AND || !N0->hasOneUse())
8160- return SDValue();
8161- SDValue N1 = Node->getOperand(1);
8162- if (N1->getOpcode() != ISD::AND || !N1->hasOneUse())
8163- return SDValue();
81648140
81658141 // If the target supports and-not, don't fold this.
81668142 if (TLI.hasAndNot(SDValue(Node, 0)))
81678143 return SDValue();
81688144
8169- SDValue N00 = N0->getOperand(0);
8170- SDValue N01 = N0->getOperand(1);
8171- SDValue N10 = N1->getOperand(0);
8172- SDValue N11 = N1->getOperand(1);
8173- if (SDValue Result = foldMaskedMergeImpl(N00, N01, N10, N11, DL, DAG))
8174- return Result;
8175- if (SDValue Result = foldMaskedMergeImpl(N01, N00, N10, N11, DL, DAG))
8176- return Result;
8177- if (SDValue Result = foldMaskedMergeImpl(N10, N11, N00, N01, DL, DAG))
8178- return Result;
8179- if (SDValue Result = foldMaskedMergeImpl(N11, N10, N00, N01, DL, DAG))
8180- return Result;
8145+ SDValue M, X, Y;
8146+ if (sd_match(Node,
8147+ m_Or(m_OneUse(m_And(m_OneUse(m_Not(m_Value(M))), m_Value(Y))),
8148+ m_OneUse(m_And(m_Deferred(M), m_Value(X)))))) {
8149+ EVT VT = M.getValueType();
8150+ SDValue Xor = DAG.getNode(ISD::XOR, DL, VT, X, Y);
8151+ SDValue And = DAG.getNode(ISD::AND, DL, VT, Xor, M);
8152+ return DAG.getNode(ISD::XOR, DL, VT, And, Y);
8153+ }
81818154 return SDValue();
81828155}
81838156
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