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[AArch64][InstCombine] Combine AES instructions with zero operands. (llvm#142781)
We currently combine (AES (EOR (A, B)), 0) into (AES A, B) for Neon intrinsics when the zero operand appears in the RHS of the AES instruction. This patch extends the combine to support AES SVE intrinsics and the case where the zero operand appears in the LHS of the AES instructions.
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‎llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp‎

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3076,10 +3076,16 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst &CI) {
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case Intrinsic::arm_neon_aesd:
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case Intrinsic::arm_neon_aese:
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case Intrinsic::aarch64_crypto_aesd:
3079-
case Intrinsic::aarch64_crypto_aese: {
3079+
case Intrinsic::aarch64_crypto_aese:
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case Intrinsic::aarch64_sve_aesd:
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case Intrinsic::aarch64_sve_aese: {
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Value *DataArg = II->getArgOperand(0);
30813083
Value *KeyArg = II->getArgOperand(1);
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// Accept zero on either operand.
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if (!match(KeyArg, m_ZeroInt()))
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std::swap(KeyArg, DataArg);
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// Try to use the builtin XOR in AESE and AESD to eliminate a prior XOR
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Value *Data, *Key;
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if (match(KeyArg, m_ZeroInt()) &&

‎llvm/test/Transforms/InstCombine/AArch64/aes-intrinsics.ll‎

Lines changed: 70 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,17 @@ define <16 x i8> @combineXorAeseZeroARM64(<16 x i8> %data, <16 x i8> %key) {
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ret <16 x i8> %data.aes
1414
}
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16+
define <16 x i8> @combineXorAeseZeroLhsARM64(<16 x i8> %data, <16 x i8> %key) {
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; CHECK-LABEL: define <16 x i8> @combineXorAeseZeroLhsARM64(
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; CHECK-SAME: <16 x i8> [[DATA:%.*]], <16 x i8> [[KEY:%.*]]) {
19+
; CHECK-NEXT: [[DATA_AES:%.*]] = tail call <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> [[DATA]], <16 x i8> [[KEY]])
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; CHECK-NEXT: ret <16 x i8> [[DATA_AES]]
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;
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%data.xor = xor <16 x i8> %data, %key
23+
%data.aes = tail call <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> zeroinitializer, <16 x i8> %data.xor)
24+
ret <16 x i8> %data.aes
25+
}
26+
1627
define <16 x i8> @combineXorAeseNonZeroARM64(<16 x i8> %data, <16 x i8> %key) {
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; CHECK-LABEL: define <16 x i8> @combineXorAeseNonZeroARM64(
1829
; CHECK-SAME: <16 x i8> [[DATA:%.*]], <16 x i8> [[KEY:%.*]]) {
@@ -36,6 +47,17 @@ define <16 x i8> @combineXorAesdZeroARM64(<16 x i8> %data, <16 x i8> %key) {
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ret <16 x i8> %data.aes
3748
}
3849

50+
define <16 x i8> @combineXorAesdZeroLhsARM64(<16 x i8> %data, <16 x i8> %key) {
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; CHECK-LABEL: define <16 x i8> @combineXorAesdZeroLhsARM64(
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; CHECK-SAME: <16 x i8> [[DATA:%.*]], <16 x i8> [[KEY:%.*]]) {
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; CHECK-NEXT: [[DATA_AES:%.*]] = tail call <16 x i8> @llvm.aarch64.crypto.aesd(<16 x i8> [[DATA]], <16 x i8> [[KEY]])
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; CHECK-NEXT: ret <16 x i8> [[DATA_AES]]
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;
56+
%data.xor = xor <16 x i8> %data, %key
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%data.aes = tail call <16 x i8> @llvm.aarch64.crypto.aesd(<16 x i8> zeroinitializer, <16 x i8> %data.xor)
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ret <16 x i8> %data.aes
59+
}
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3961
define <16 x i8> @combineXorAesdNonZeroARM64(<16 x i8> %data, <16 x i8> %key) {
4062
; CHECK-LABEL: define <16 x i8> @combineXorAesdNonZeroARM64(
4163
; CHECK-SAME: <16 x i8> [[DATA:%.*]], <16 x i8> [[KEY:%.*]]) {
@@ -51,3 +73,51 @@ define <16 x i8> @combineXorAesdNonZeroARM64(<16 x i8> %data, <16 x i8> %key) {
5173
declare <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8>, <16 x i8>) #0
5274
declare <16 x i8> @llvm.aarch64.crypto.aesd(<16 x i8>, <16 x i8>) #0
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76+
; SVE
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define <vscale x 16 x i8> @combineXorAeseZeroLhsSVE(<vscale x 16 x i8> %data, <vscale x 16 x i8> %key) {
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; CHECK-LABEL: define <vscale x 16 x i8> @combineXorAeseZeroLhsSVE(
80+
; CHECK-SAME: <vscale x 16 x i8> [[DATA:%.*]], <vscale x 16 x i8> [[KEY:%.*]]) {
81+
; CHECK-NEXT: [[DATA_AES:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.aese(<vscale x 16 x i8> [[DATA]], <vscale x 16 x i8> [[KEY]])
82+
; CHECK-NEXT: ret <vscale x 16 x i8> [[DATA_AES]]
83+
;
84+
%data.xor = xor <vscale x 16 x i8> %data, %key
85+
%data.aes = tail call <vscale x 16 x i8> @llvm.aarch64.sve.aese(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i8> %data.xor)
86+
ret <vscale x 16 x i8> %data.aes
87+
}
88+
89+
define <vscale x 16 x i8> @combineXorAeseZeroRhsSVE(<vscale x 16 x i8> %data, <vscale x 16 x i8> %key) {
90+
; CHECK-LABEL: define <vscale x 16 x i8> @combineXorAeseZeroRhsSVE(
91+
; CHECK-SAME: <vscale x 16 x i8> [[DATA:%.*]], <vscale x 16 x i8> [[KEY:%.*]]) {
92+
; CHECK-NEXT: [[DATA_AES:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.aese(<vscale x 16 x i8> [[DATA]], <vscale x 16 x i8> [[KEY]])
93+
; CHECK-NEXT: ret <vscale x 16 x i8> [[DATA_AES]]
94+
;
95+
%data.xor = xor <vscale x 16 x i8> %data, %key
96+
%data.aes = tail call <vscale x 16 x i8> @llvm.aarch64.sve.aese(<vscale x 16 x i8> %data.xor, <vscale x 16 x i8> zeroinitializer)
97+
ret <vscale x 16 x i8> %data.aes
98+
}
99+
100+
define <vscale x 16 x i8> @combineXorAesdZeroLhsSVE(<vscale x 16 x i8> %data, <vscale x 16 x i8> %key) {
101+
; CHECK-LABEL: define <vscale x 16 x i8> @combineXorAesdZeroLhsSVE(
102+
; CHECK-SAME: <vscale x 16 x i8> [[DATA:%.*]], <vscale x 16 x i8> [[KEY:%.*]]) {
103+
; CHECK-NEXT: [[DATA_AES:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.aesd(<vscale x 16 x i8> [[DATA]], <vscale x 16 x i8> [[KEY]])
104+
; CHECK-NEXT: ret <vscale x 16 x i8> [[DATA_AES]]
105+
;
106+
%data.xor = xor <vscale x 16 x i8> %data, %key
107+
%data.aes = tail call <vscale x 16 x i8> @llvm.aarch64.sve.aesd(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i8> %data.xor)
108+
ret <vscale x 16 x i8> %data.aes
109+
}
110+
111+
define <vscale x 16 x i8> @combineXorAesdZeroRhsSVE(<vscale x 16 x i8> %data, <vscale x 16 x i8> %key) {
112+
; CHECK-LABEL: define <vscale x 16 x i8> @combineXorAesdZeroRhsSVE(
113+
; CHECK-SAME: <vscale x 16 x i8> [[DATA:%.*]], <vscale x 16 x i8> [[KEY:%.*]]) {
114+
; CHECK-NEXT: [[DATA_AES:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.aesd(<vscale x 16 x i8> [[DATA]], <vscale x 16 x i8> [[KEY]])
115+
; CHECK-NEXT: ret <vscale x 16 x i8> [[DATA_AES]]
116+
;
117+
%data.xor = xor <vscale x 16 x i8> %data, %key
118+
%data.aes = tail call <vscale x 16 x i8> @llvm.aarch64.sve.aesd(<vscale x 16 x i8> %data.xor, <vscale x 16 x i8> zeroinitializer)
119+
ret <vscale x 16 x i8> %data.aes
120+
}
121+
122+
declare <vscale x 16 x i8> @llvm.aarch64.sve.aese(<vscale x 16 x i8>, <vscale x 16 x i8>) #0
123+
declare <vscale x 16 x i8> @llvm.aarch64.sve.aesd(<vscale x 16 x i8>, <vscale x 16 x i8>) #0

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