Disable '<=' for VHDL use

[ghost]

I use Fira Code w/ ligatures enabled on VS Code.

However, I mainly use a language called VHDL. In VHDL the operator '<= ' is not use for comparison.

Is there a way that I can edit ligatures to either ignore only the '<=' rendering? Ideally I would like to make '<=' appear just like '=>' but pointing to the left. However, just having VS Code ignore the ligature rendering of '<=' would be great!

Thanks!

[tonsky]

Not at the moment, but eventually I plan to have a configurator. Can’t promise when, though