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[CodeGen] Change copyPhysReg interface to use Register instead of MCRegister.
NVPTX, SPIRV, and WebAssembly pass virtual registers to this function since they don't perform register allocation. We need to use Register to avoid a virtual register being converted to MCRegister by the caller. This is an alternative to llvm#128456.
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57 files changed

+92
-93
lines changed

‎llvm/include/llvm/CodeGen/TargetInstrInfo.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1035,7 +1035,7 @@ class TargetInstrInfo : public MCInstrInfo {
10351035
/// marked renamable.
10361036
virtual void copyPhysReg(MachineBasicBlock &MBB,
10371037
MachineBasicBlock::iterator MI, const DebugLoc &DL,
1038-
MCRegister DestReg, MCRegister SrcReg, bool KillSrc,
1038+
Register DestReg, Register SrcReg, bool KillSrc,
10391039
bool RenamableDest = false,
10401040
bool RenamableSrc = false) const {
10411041
llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4988,8 +4988,8 @@ void AArch64InstrInfo::copyGPRRegTuple(MachineBasicBlock &MBB,
49884988

49894989
void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
49904990
MachineBasicBlock::iterator I,
4991-
const DebugLoc &DL, MCRegister DestReg,
4992-
MCRegister SrcReg, bool KillSrc,
4991+
const DebugLoc &DL, Register DestReg,
4992+
Register SrcReg, bool KillSrc,
49934993
bool RenamableDest,
49944994
bool RenamableSrc) const {
49954995
if (AArch64::GPR32spRegClass.contains(DestReg) &&
@@ -5068,8 +5068,8 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
50685068
auto ToPPR = [](MCRegister R) -> MCRegister {
50695069
return (R - AArch64::PN0) + AArch64::P0;
50705070
};
5071-
MCRegister PPRSrcReg = SrcIsPNR ? ToPPR(SrcReg) : SrcReg;
5072-
MCRegister PPRDestReg = DestIsPNR ? ToPPR(DestReg) : DestReg;
5071+
MCRegister PPRSrcReg = SrcIsPNR ? ToPPR(SrcReg) : SrcReg.asMCReg();
5072+
MCRegister PPRDestReg = DestIsPNR ? ToPPR(DestReg) : DestReg.asMCReg();
50735073

50745074
if (PPRSrcReg != PPRDestReg) {
50755075
auto NewMI = BuildMI(MBB, I, DL, get(AArch64::ORR_PPzPP), PPRDestReg)

‎llvm/lib/Target/AArch64/AArch64InstrInfo.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -343,7 +343,7 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
343343
bool KillSrc, unsigned Opcode, unsigned ZeroReg,
344344
llvm::ArrayRef<unsigned> Indices) const;
345345
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
346-
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
346+
const DebugLoc &DL, Register DestReg, Register SrcReg,
347347
bool KillSrc, bool RenamableDest = false,
348348
bool RenamableSrc = false) const override;
349349

‎llvm/lib/Target/AMDGPU/R600InstrInfo.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -37,8 +37,8 @@ bool R600InstrInfo::isVector(const MachineInstr &MI) const {
3737

3838
void R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3939
MachineBasicBlock::iterator MI,
40-
const DebugLoc &DL, MCRegister DestReg,
41-
MCRegister SrcReg, bool KillSrc,
40+
const DebugLoc &DL, Register DestReg,
41+
Register SrcReg, bool KillSrc,
4242
bool RenamableDest, bool RenamableSrc) const {
4343
unsigned VectorComponents = 0;
4444
if ((R600::R600_Reg128RegClass.contains(DestReg) ||

‎llvm/lib/Target/AMDGPU/R600InstrInfo.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -73,7 +73,7 @@ class R600InstrInfo final : public R600GenInstrInfo {
7373
}
7474

7575
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
76-
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
76+
const DebugLoc &DL, Register DestReg, Register SrcReg,
7777
bool KillSrc, bool RenamableDest = false,
7878
bool RenamableSrc = false) const override;
7979
bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,

‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -801,9 +801,9 @@ static void expandSGPRCopy(const SIInstrInfo &TII, MachineBasicBlock &MBB,
801801

802802
void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
803803
MachineBasicBlock::iterator MI,
804-
const DebugLoc &DL, MCRegister DestReg,
805-
MCRegister SrcReg, bool KillSrc,
806-
bool RenamableDest, bool RenamableSrc) const {
804+
const DebugLoc &DL, Register DestReg,
805+
Register SrcReg, bool KillSrc, bool RenamableDest,
806+
bool RenamableSrc) const {
807807
const TargetRegisterClass *RC = RI.getPhysRegBaseClass(DestReg);
808808
unsigned Size = RI.getRegSizeInBits(*RC);
809809
const TargetRegisterClass *SrcRC = RI.getPhysRegBaseClass(SrcReg);
@@ -816,7 +816,7 @@ void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
816816
if (((Size == 16) != (SrcSize == 16))) {
817817
// Non-VGPR Src and Dst will later be expanded back to 32 bits.
818818
assert(ST.hasTrue16BitInsts());
819-
MCRegister &RegToFix = (Size == 32) ? DestReg : SrcReg;
819+
Register &RegToFix = (Size == 32) ? DestReg : SrcReg;
820820
MCRegister SubReg = RI.getSubReg(RegToFix, AMDGPU::lo16);
821821
RegToFix = SubReg;
822822

‎llvm/lib/Target/AMDGPU/SIInstrInfo.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -263,7 +263,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
263263
int64_t Offset1, unsigned NumLoads) const override;
264264

265265
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
266-
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
266+
const DebugLoc &DL, Register DestReg, Register SrcReg,
267267
bool KillSrc, bool RenamableDest = false,
268268
bool RenamableSrc = false) const override;
269269

‎llvm/lib/Target/ARC/ARCInstrInfo.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -280,8 +280,8 @@ unsigned ARCInstrInfo::removeBranch(MachineBasicBlock &MBB,
280280

281281
void ARCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
282282
MachineBasicBlock::iterator I,
283-
const DebugLoc &DL, MCRegister DestReg,
284-
MCRegister SrcReg, bool KillSrc,
283+
const DebugLoc &DL, Register DestReg,
284+
Register SrcReg, bool KillSrc,
285285
bool RenamableDest, bool RenamableSrc) const {
286286
assert(ARC::GPR32RegClass.contains(SrcReg) &&
287287
"Only GPR32 src copy supported.");

‎llvm/lib/Target/ARC/ARCInstrInfo.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -64,7 +64,7 @@ class ARCInstrInfo : public ARCGenInstrInfo {
6464
int *BytesRemoved = nullptr) const override;
6565

6666
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
67-
const DebugLoc &, MCRegister DestReg, MCRegister SrcReg,
67+
const DebugLoc &, Register DestReg, Register SrcReg,
6868
bool KillSrc, bool RenamableDest = false,
6969
bool RenamableSrc = false) const override;
7070

‎llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -889,8 +889,8 @@ void llvm::addPredicatedMveVpredROp(MachineInstrBuilder &MIB,
889889

890890
void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
891891
MachineBasicBlock::iterator I,
892-
const DebugLoc &DL, MCRegister DestReg,
893-
MCRegister SrcReg, bool KillSrc,
892+
const DebugLoc &DL, Register DestReg,
893+
Register SrcReg, bool KillSrc,
894894
bool RenamableDest,
895895
bool RenamableSrc) const {
896896
bool GPRDest = ARM::GPRRegClass.contains(DestReg);

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