[RISCV] Use shiftop<rotl> in one of the BCLR patterns.

This allows us to remove AND from the shift amount when DAG combine
has replaced (not (shl 1, X)) with (rotl -2, X). SimplifyDemandedBits
will often simplify the rotl case on its own, but not if the masked
shift amount has multiple users.

This will need to be rebase if llvm#164050 goes in first.

Author: topperc

llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

@@ -527,7 +527,7 @@ def : Pat<(riscv_rolw GPR:$rs1, uimm5:$rs2),
 let Predicates = [HasStdExtZbs] in {
 def : Pat<(XLenVT (and (not (shiftop<shl> 1, (XLenVT GPR:$rs2))), GPR:$rs1)),
           (BCLR GPR:$rs1, GPR:$rs2)>;
-def : Pat<(XLenVT (and (rotl -2, (XLenVT GPR:$rs2)), GPR:$rs1)),
+def : Pat<(XLenVT (and (shiftop<rotl> -2, (XLenVT GPR:$rs2)), GPR:$rs1)),
           (BCLR GPR:$rs1, GPR:$rs2)>;
 def : Pat<(XLenVT (or (shiftop<shl> 1, (XLenVT GPR:$rs2)), GPR:$rs1)),
           (BSET GPR:$rs1, GPR:$rs2)>;

llvm/test/CodeGen/RISCV/rv32zbs.ll

@@ -56,20 +56,12 @@ define i32 @bclr_i32_mask_multiple(i32 %a, i32 %b, i32 %shamt) nounwind {
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
-; RV32ZBSNOZBB-LABEL: bclr_i32_mask_multiple:
-; RV32ZBSNOZBB:       # %bb.0:
-; RV32ZBSNOZBB-NEXT:    bclr a0, a0, a2
-; RV32ZBSNOZBB-NEXT:    bset a1, a1, a2
-; RV32ZBSNOZBB-NEXT:    add a0, a0, a1
-; RV32ZBSNOZBB-NEXT:    ret
-;
-; RV32ZBSZBB-LABEL: bclr_i32_mask_multiple:
-; RV32ZBSZBB:       # %bb.0:
-; RV32ZBSZBB-NEXT:    andi a3, a2, 63
-; RV32ZBSZBB-NEXT:    bclr a0, a0, a3
-; RV32ZBSZBB-NEXT:    bset a1, a1, a2
-; RV32ZBSZBB-NEXT:    add a0, a0, a1
-; RV32ZBSZBB-NEXT:    ret
+; RV32ZBS-LABEL: bclr_i32_mask_multiple:
+; RV32ZBS:       # %bb.0:
+; RV32ZBS-NEXT:    bclr a0, a0, a2
+; RV32ZBS-NEXT:    bset a1, a1, a2
+; RV32ZBS-NEXT:    add a0, a0, a1
+; RV32ZBS-NEXT:    ret
   %shamt_masked = and i32 %shamt, 63
   %shl = shl nuw i32 1, %shamt_masked
   %neg = xor i32 %shl, -1

llvm/test/CodeGen/RISCV/rv64zbs.ll

@@ -2,9 +2,9 @@
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefixes=CHECK,RV64I
 ; RUN: llc -mtriple=riscv64 -mattr=+zbs -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefixes=CHECK,RV64ZBS,RV64ZBSNOZBB
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV64ZBS
 ; RUN: llc -mtriple=riscv64 -mattr=+zbs,+zbb -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefixes=CHECK,RV64ZBS,RV64ZBSZBB
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV64ZBS
 
 define signext i32 @bclr_i32(i32 signext %a, i32 signext %b) nounwind {
 ; RV64I-LABEL: bclr_i32:
@@ -121,20 +121,12 @@ define i64 @bclr_i64_mask_multiple(i64 %a, i64 %b, i64 %shamt) nounwind {
 ; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBSNOZBB-LABEL: bclr_i64_mask_multiple:
-; RV64ZBSNOZBB:       # %bb.0:
-; RV64ZBSNOZBB-NEXT:    bclr a0, a0, a2
-; RV64ZBSNOZBB-NEXT:    bset a1, a1, a2
-; RV64ZBSNOZBB-NEXT:    add a0, a0, a1
-; RV64ZBSNOZBB-NEXT:    ret
-;
-; RV64ZBSZBB-LABEL: bclr_i64_mask_multiple:
-; RV64ZBSZBB:       # %bb.0:
-; RV64ZBSZBB-NEXT:    andi a3, a2, 63
-; RV64ZBSZBB-NEXT:    bclr a0, a0, a3
-; RV64ZBSZBB-NEXT:    bset a1, a1, a2
-; RV64ZBSZBB-NEXT:    add a0, a0, a1
-; RV64ZBSZBB-NEXT:    ret
+; RV64ZBS-LABEL: bclr_i64_mask_multiple:
+; RV64ZBS:       # %bb.0:
+; RV64ZBS-NEXT:    bclr a0, a0, a2
+; RV64ZBS-NEXT:    bset a1, a1, a2
+; RV64ZBS-NEXT:    add a0, a0, a1
+; RV64ZBS-NEXT:    ret
   %shamt_masked = and i64 %shamt, 63
   %shl = shl nuw i64 1, %shamt_masked
   %neg = xor i64 %shl, -1