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[RISCV] Split OPERAND_SEW operand type for mask only instructions.
Mask only instructions like vmand and vmsbf should always have 0 for their Log2SEW operand. Non-mask instructions should only have 3, 4, 5, or 6 for their Log2SEW operand. Split the operand type so we can verify these cases separately. I had to fix the SEW for whole register move to vmv.v.v copy optimization and update an mir test. The vmv.v.v change isn't functional since we have already done vsetvli insertion before and nothing else uses the field after copy expansion. I can split these changes off if desired. Stacked on llvm#119767.
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-26
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4 files changed

+44
-26
lines changed

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -346,8 +346,10 @@ enum OperandType : unsigned {
346346
OPERAND_COND_CODE,
347347
// Vector policy operand.
348348
OPERAND_VEC_POLICY,
349-
// Vector SEW operand.
349+
// Vector SEW operand. Stores in log2(SEW).
350350
OPERAND_SEW,
351+
// Special SEW for mask only instructions. Always 0.
352+
OPERAND_SEW_MASK,
351353
// Vector rounding mode for VXRM or FRM.
352354
OPERAND_VEC_RM,
353355
OPERAND_LAST_RISCV_IMM = OPERAND_VEC_RM,

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp‎

Lines changed: 9 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -430,7 +430,9 @@ void RISCVInstrInfo::copyPhysRegVector(
430430
if (UseVMV) {
431431
const MCInstrDesc &Desc = DefMBBI->getDesc();
432432
MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc))); // AVL
433-
MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW
433+
unsigned Log2SEW =
434+
DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc)).getImm();
435+
MIB.addImm(Log2SEW ? Log2SEW : 3); // SEW
434436
MIB.addImm(0); // tu, mu
435437
MIB.addReg(RISCV::VL, RegState::Implicit);
436438
MIB.addReg(RISCV::VTYPE, RegState::Implicit);
@@ -2568,7 +2570,10 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
25682570
Ok = (Imm & (RISCVII::TAIL_AGNOSTIC | RISCVII::MASK_AGNOSTIC)) == Imm;
25692571
break;
25702572
case RISCVOp::OPERAND_SEW:
2571-
Ok = Imm == 0 || (isUInt<5>(Imm) && RISCVVType::isValidSEW(1 << Imm));
2573+
Ok = (isUInt<5>(Imm) && RISCVVType::isValidSEW(1 << Imm));
2574+
break;
2575+
case RISCVOp::OPERAND_SEW_MASK:
2576+
Ok = Imm == 0;
25722577
break;
25732578
case RISCVOp::OPERAND_VEC_RM:
25742579
assert(RISCVII::hasRoundModeOp(Desc.TSFlags));
@@ -3206,7 +3211,8 @@ std::string RISCVInstrInfo::createMIROperandComment(
32063211
RISCVVType::printVType(Imm, OS);
32073212
break;
32083213
}
3209-
case RISCVOp::OPERAND_SEW: {
3214+
case RISCVOp::OPERAND_SEW:
3215+
case RISCVOp::OPERAND_SEW_MASK: {
32103216
unsigned Log2SEW = Op.getImm();
32113217
unsigned SEW = Log2SEW ? 1 << Log2SEW : 8;
32123218
assert(RISCVVType::isValidSEW(SEW) && "Unexpected SEW");

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td‎

Lines changed: 26 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -92,6 +92,11 @@ def sew : RISCVOp {
9292
let OperandType = "OPERAND_SEW";
9393
}
9494

95+
// SEW for mask only instructions like vmand and vmsbf. Should always be 0.
96+
def sew_mask : RISCVOp {
97+
let OperandType = "OPERAND_SEW_MASK";
98+
}
99+
95100
def vec_rm : RISCVOp {
96101
let OperandType = "OPERAND_VEC_RM";
97102
}
@@ -774,9 +779,10 @@ class GetVTypePredicates<VTypeInfo vti> {
774779
}
775780

776781
class VPseudoUSLoadNoMask<VReg RetClass,
777-
int EEW> :
782+
int EEW,
783+
DAGOperand sewop = sew> :
778784
Pseudo<(outs RetClass:$rd),
779-
(ins RetClass:$dest, GPRMem:$rs1, AVL:$vl, sew:$sew,
785+
(ins RetClass:$dest, GPRMem:$rs1, AVL:$vl, sewop:$sew,
780786
vec_policy:$policy), []>,
781787
RISCVVPseudo,
782788
RISCVVLE</*Masked*/0, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
@@ -922,9 +928,10 @@ class VPseudoILoadMask<VReg RetClass,
922928
}
923929

924930
class VPseudoUSStoreNoMask<VReg StClass,
925-
int EEW> :
931+
int EEW,
932+
DAGOperand sewop = sew> :
926933
Pseudo<(outs),
927-
(ins StClass:$rd, GPRMem:$rs1, AVL:$vl, sew:$sew), []>,
934+
(ins StClass:$rd, GPRMem:$rs1, AVL:$vl, sewop:$sew), []>,
928935
RISCVVPseudo,
929936
RISCVVSE</*Masked*/0, /*Strided*/0, !logtwo(EEW), VLMul> {
930937
let mayLoad = 0;
@@ -1008,7 +1015,7 @@ class VPseudoNullaryMask<VReg RegClass> :
10081015
// Nullary for pseudo instructions. They are expanded in
10091016
// RISCVExpandPseudoInsts pass.
10101017
class VPseudoNullaryPseudoM<string BaseInst> :
1011-
Pseudo<(outs VR:$rd), (ins AVL:$vl, sew:$sew), []>,
1018+
Pseudo<(outs VR:$rd), (ins AVL:$vl, sew_mask:$sew), []>,
10121019
RISCVVPseudo {
10131020
let mayLoad = 0;
10141021
let mayStore = 0;
@@ -1045,7 +1052,7 @@ class VPseudoUnaryNoMaskNoPolicy<DAGOperand RetClass,
10451052
string Constraint = "",
10461053
bits<2> TargetConstraintType = 1> :
10471054
Pseudo<(outs RetClass:$rd),
1048-
(ins OpClass:$rs2, AVL:$vl, sew:$sew), []>,
1055+
(ins OpClass:$rs2, AVL:$vl, sew_mask:$sew), []>,
10491056
RISCVVPseudo {
10501057
let mayLoad = 0;
10511058
let mayStore = 0;
@@ -1080,10 +1087,11 @@ class VPseudoUnaryNoMaskRoundingMode<DAGOperand RetClass,
10801087
class VPseudoUnaryMask<VReg RetClass,
10811088
VReg OpClass,
10821089
string Constraint = "",
1083-
bits<2> TargetConstraintType = 1> :
1090+
bits<2> TargetConstraintType = 1,
1091+
DAGOperand sewop = sew> :
10841092
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
10851093
(ins GetVRegNoV0<RetClass>.R:$passthru, OpClass:$rs2,
1086-
VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
1094+
VMaskOp:$vm, AVL:$vl, sewop:$sew, vec_policy:$policy), []>,
10871095
RISCVVPseudo {
10881096
let mayLoad = 0;
10891097
let mayStore = 0;
@@ -1138,7 +1146,7 @@ class VPseudoUnaryMask_NoExcept<VReg RetClass,
11381146

11391147
class VPseudoUnaryNoMaskGPROut :
11401148
Pseudo<(outs GPR:$rd),
1141-
(ins VR:$rs2, AVL:$vl, sew:$sew), []>,
1149+
(ins VR:$rs2, AVL:$vl, sew_mask:$sew), []>,
11421150
RISCVVPseudo {
11431151
let mayLoad = 0;
11441152
let mayStore = 0;
@@ -1149,7 +1157,7 @@ class VPseudoUnaryNoMaskGPROut :
11491157

11501158
class VPseudoUnaryMaskGPROut :
11511159
Pseudo<(outs GPR:$rd),
1152-
(ins VR:$rs1, VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
1160+
(ins VR:$rs1, VMaskOp:$vm, AVL:$vl, sew_mask:$sew), []>,
11531161
RISCVVPseudo {
11541162
let mayLoad = 0;
11551163
let mayStore = 0;
@@ -1177,9 +1185,10 @@ class VPseudoBinaryNoMask<VReg RetClass,
11771185
VReg Op1Class,
11781186
DAGOperand Op2Class,
11791187
string Constraint,
1180-
bits<2> TargetConstraintType = 1> :
1188+
bits<2> TargetConstraintType = 1,
1189+
DAGOperand sewop = sew> :
11811190
Pseudo<(outs RetClass:$rd),
1182-
(ins Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, sew:$sew), []>,
1191+
(ins Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, sewop:$sew), []>,
11831192
RISCVVPseudo {
11841193
let mayLoad = 0;
11851194
let mayStore = 0;
@@ -1852,7 +1861,7 @@ multiclass VPseudoLoadMask {
18521861
defvar mx = mti.LMul.MX;
18531862
defvar WriteVLDM_MX = !cast<SchedWrite>("WriteVLDM_" # mx);
18541863
let VLMul = mti.LMul.value in {
1855-
def "_V_" # mti.BX : VPseudoUSLoadNoMask<VR, EEW=1>,
1864+
def "_V_" # mti.BX : VPseudoUSLoadNoMask<VR, EEW=1, sewop=sew_mask>,
18561865
Sched<[WriteVLDM_MX, ReadVLDX]>;
18571866
}
18581867
}
@@ -1927,7 +1936,7 @@ multiclass VPseudoStoreMask {
19271936
defvar mx = mti.LMul.MX;
19281937
defvar WriteVSTM_MX = !cast<SchedWrite>("WriteVSTM_" # mx);
19291938
let VLMul = mti.LMul.value in {
1930-
def "_V_" # mti.BX : VPseudoUSStoreNoMask<VR, EEW=1>,
1939+
def "_V_" # mti.BX : VPseudoUSStoreNoMask<VR, EEW=1, sewop=sew_mask>,
19311940
Sched<[WriteVSTM_MX, ReadVSTX]>;
19321941
}
19331942
}
@@ -2011,7 +2020,8 @@ multiclass VPseudoVSFS_M {
20112020
SchedUnary<"WriteVMSFSV", "ReadVMSFSV", mx,
20122021
forcePassthruRead=true>;
20132022
let ForceTailAgnostic = true in
2014-
def "_M_" # mti.BX # "_MASK" : VPseudoUnaryMask<VR, VR, constraint>,
2023+
def "_M_" # mti.BX # "_MASK" : VPseudoUnaryMask<VR, VR, constraint,
2024+
sewop = sew_mask>,
20152025
SchedUnary<"WriteVMSFSV", "ReadVMSFSV", mx,
20162026
forcePassthruRead=true>;
20172027
}
@@ -2269,7 +2279,7 @@ multiclass VPseudoVALU_MM<bit Commutable = 0> {
22692279
foreach m = MxList in {
22702280
defvar mx = m.MX;
22712281
let VLMul = m.value, isCommutable = Commutable in {
2272-
def "_MM_" # mx : VPseudoBinaryNoMask<VR, VR, VR, "">,
2282+
def "_MM_" # mx : VPseudoBinaryNoMask<VR, VR, VR, "", sewop = sew_mask>,
22732283
SchedBinary<"WriteVMALUV", "ReadVMALUV", "ReadVMALUV", mx>;
22742284
}
22752285
}

‎llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -13,12 +13,12 @@ body: |
1313
; CHECK-NEXT: %false:vr = COPY $v8
1414
; CHECK-NEXT: %true:vr = COPY $v9
1515
; CHECK-NEXT: %avl:gprnox0 = COPY $x1
16-
; CHECK-NEXT: %mask:vmv0 = PseudoVMSET_M_B8 %avl, 5 /* e32 */
16+
; CHECK-NEXT: %mask:vmv0 = PseudoVMSET_M_B8 %avl, 0 /* e8 */
1717
; CHECK-NEXT: $v0 = COPY %mask
1818
%false:vr = COPY $v8
1919
%true:vr = COPY $v9
2020
%avl:gprnox0 = COPY $x1
21-
%mask:vmv0 = PseudoVMSET_M_B8 %avl, 5
21+
%mask:vmv0 = PseudoVMSET_M_B8 %avl, 0
2222
$v0 = COPY %mask
2323
%x:vrnov0 = PseudoVMERGE_VVM_M1 $noreg, %false, %true, $v0, %avl, 5
2424
...
@@ -34,14 +34,14 @@ body: |
3434
; CHECK-NEXT: %false:vr = COPY $noreg
3535
; CHECK-NEXT: %true:vr = COPY $v9
3636
; CHECK-NEXT: %avl:gprnox0 = COPY $x1
37-
; CHECK-NEXT: %mask:vmv0 = PseudoVMSET_M_B8 %avl, 5 /* e32 */
37+
; CHECK-NEXT: %mask:vmv0 = PseudoVMSET_M_B8 %avl, 0 /* e8 */
3838
; CHECK-NEXT: $v0 = COPY %mask
3939
; CHECK-NEXT: %x:vr = PseudoVMV_V_V_M1 %pt, %true, %avl, 5 /* e32 */, 0 /* tu, mu */
4040
%pt:vrnov0 = COPY $v8
4141
%false:vr = COPY $noreg
4242
%true:vr = COPY $v9
4343
%avl:gprnox0 = COPY $x1
44-
%mask:vmv0 = PseudoVMSET_M_B8 %avl, 5
44+
%mask:vmv0 = PseudoVMSET_M_B8 %avl, 0
4545
$v0 = COPY %mask
4646
%x:vrnov0 = PseudoVMERGE_VVM_M1 %pt, %false, %true, $v0, %avl, 5
4747
...
@@ -57,14 +57,14 @@ body: |
5757
; CHECK-NEXT: %pt:vr = COPY $v8
5858
; CHECK-NEXT: %true:vr = COPY $v9
5959
; CHECK-NEXT: %avl:gprnox0 = COPY $x1
60-
; CHECK-NEXT: %mask:vmv0 = PseudoVMSET_M_B8 %avl, 5 /* e32 */
60+
; CHECK-NEXT: %mask:vmv0 = PseudoVMSET_M_B8 %avl, 0 /* e8 */
6161
; CHECK-NEXT: $v0 = COPY %mask
6262
; CHECK-NEXT: %x:vr = PseudoVMV_V_V_M1 %pt, %true, %avl, 5 /* e32 */, 0 /* tu, mu */
6363
%false:vr = COPY $v8
6464
%pt:vrnov0 = COPY $v8
6565
%true:vr = COPY $v9
6666
%avl:gprnox0 = COPY $x1
67-
%mask:vmv0 = PseudoVMSET_M_B8 %avl, 5
67+
%mask:vmv0 = PseudoVMSET_M_B8 %avl, 0
6868
$v0 = COPY %mask
6969
%x:vrnov0 = PseudoVMERGE_VVM_M1 %pt, %false, %true, $v0, %avl, 5
7070
...

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