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lattice: fixed SRAM for NEXUS family
1 parent 6f92036 commit 2c6dac2

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2 files changed

+104
-45
lines changed

2 files changed

+104
-45
lines changed

‎src/lattice.cpp‎

Lines changed: 103 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,9 @@ using namespace std;
3333
# define ISC_ENABLE_FLASH_MODE (1 << 3)
3434
# define ISC_ENABLE_SRAM_MODE (0 << 3)
3535
#define ISC_ENABLE_TRANSPARENT 0x74 /* ISC_ENABLE_X This command is used to put the device in transparent mode */
36+
#define LSC_BITSTREAM_BURST 0x7A /* Program the device with the */
37+
/* bitstream sent in through the */
38+
/* JTAG port. */
3639
#define ISC_DISABLE 0x26 /* ISC_DISABLE */
3740
#define READ_DEVICE_ID_CODE 0xE0 /* IDCODE_PUB */
3841
#define FLASH_ERASE 0x0E /* ISC_ERASE */
@@ -156,6 +159,9 @@ using namespace std;
156159
#define ECP3_LSCC_REFRESH 0x23
157160
#define ECP3_READ_STATUS_REGISTER 0x53
158161

162+
/* Nexus */
163+
#define REG_NEXUS_STATUS_BSE_ERR_MASK (0x0f << 24)
164+
159165
Lattice::Lattice(Jtag *jtag, const string filename, const string &file_type,
160166
Device::prog_type_t prg_type, std::string flash_sector, bool verify, int8_t verbose, bool skip_load_bridge, bool skip_reset):
161167
Device(jtag, filename, file_type, verify, verbose),
@@ -284,6 +290,43 @@ bool Lattice::checkStatus(uint64_t val, uint64_t mask)
284290
return ((reg & mask) == val) ? true : false;
285291
}
286292

293+
/* PRELOAD/SAMPLE 0x1C
294+
* For NEXUS family fpgas, the Bscan register is 362 bits long or
295+
* 45.25 bytes => 46 bytes
296+
* For ECP3 family fpgas, the Bscan register is 1077 bits long or
297+
* 134.62 bytes => 135 bytes
298+
*/
299+
bool Lattice::preload()
300+
{
301+
uint8_t tx_buf[135];
302+
memset(tx_buf, 0xff, 135);
303+
int tx_len;
304+
int tx_bit_len;
305+
switch (_fpga_family) {
306+
case ECP3_FAMILY:
307+
tx_len = 135;
308+
tx_bit_len = 1077;
309+
break;
310+
case NEXUS_FAMILY:
311+
tx_len = 46;
312+
tx_bit_len = 362;
313+
break;
314+
default:
315+
tx_len = 26;
316+
tx_bit_len = tx_len * 8;
317+
}
318+
if(_fpga_family == NEXUS_FAMILY){
319+
uint8_t cmd = PRELOAD_SAMPLE;
320+
_jtag->shiftIR(&cmd, NULL, 8, Jtag::RUN_TEST_IDLE);
321+
_jtag->shiftDR(tx_buf, NULL, tx_bit_len,
322+
Jtag::RUN_TEST_IDLE);
323+
} else {
324+
wr_rd(PRELOAD_SAMPLE, tx_buf, tx_len, NULL, 0);
325+
}
326+
327+
return true;
328+
}
329+
287330
bool Lattice::program_mem()
288331
{
289332
bool err;
@@ -329,20 +372,7 @@ bool Lattice::program_mem()
329372
* For ECP3 family fpgas, the Bscan register is 1077 bits long or
330373
* 134.62 bytes => 135 bytes
331374
*/
332-
uint8_t tx_buf[135];
333-
memset(tx_buf, 0xff, 135);
334-
int tx_len;
335-
switch (_fpga_family) {
336-
case NEXUS_FAMILY:
337-
tx_len = 46;
338-
break;
339-
case ECP3_FAMILY:
340-
tx_len = 135;
341-
break;
342-
default:
343-
tx_len = 26;
344-
}
345-
wr_rd(PRELOAD_SAMPLE, tx_buf, tx_len, NULL, 0);
375+
preload();
346376

347377
/* LSC_REFRESH 0x79 -- "Equivalent to toggle PROGRAMN pin"
348378
* We REFRESH only if the fpga is in a status of error due to
@@ -353,29 +383,29 @@ bool Lattice::program_mem()
353383
bool was_refreshed;
354384
switch (_fpga_family) {
355385
case NEXUS_FAMILY:
356-
if (!checkStatus(0, REG_STATUS_PRV_CNF_CHK_MASK)) {
357-
printInfo("Error in previous bitstream execution. REFRESH: ", false);
358-
wr_rd(REFRESH, NULL, 0, NULL, 0);
359-
_jtag->set_state(Jtag::RUN_TEST_IDLE);
360-
_jtag->toggleClk(1000);
361-
/* In Lattice FPGA-TN-02099 document in a note it's reported that there
362-
is a delay time after LSC_REFRESH where "Duration could be in
363-
seconds". Without whis waiting time, busy flag can't be cleared.*/
364-
sleep(5);
365-
was_refreshed = true;
366-
if (!checkStatus(0, REG_STATUS_PRV_CNF_CHK_MASK)) {
367-
printError("FAIL");
368-
displayReadReg(readStatusReg());
369-
return false;
370-
} else {
371-
printSuccess("DONE");
372-
}
373-
} else {
374-
was_refreshed = false;
375-
if (_verbose){
376-
printInfo("No error in previous bitstream execution.", true);
377-
}
378-
}
386+
//if (!checkStatus(0, REG_STATUS_PRV_CNF_CHK_MASK)) {
387+
// printInfo("Error in previous bitstream execution. REFRESH: ", false);
388+
// wr_rd(REFRESH, NULL, 0, NULL, 0);
389+
// _jtag->set_state(Jtag::RUN_TEST_IDLE);
390+
// _jtag->toggleClk(1000);
391+
// /* In Lattice FPGA-TN-02099 document in a note it's reported that there
392+
// is a delay time after LSC_REFRESH where "Duration could be in
393+
// seconds". Without whis waiting time, busy flag can't be cleared.*/
394+
// sleep(5);
395+
// was_refreshed = true;
396+
// if (!checkStatus(0, REG_STATUS_PRV_CNF_CHK_MASK)) {
397+
// printError("FAIL");
398+
// displayReadReg(readStatusReg());
399+
// return false;
400+
// } else {
401+
// printSuccess("DONE");
402+
// }
403+
//} else {
404+
// was_refreshed = false;
405+
// if (_verbose){
406+
// printInfo("No error in previous bitstream execution.", true);
407+
// }
408+
//}
379409
break;
380410
case ECP3_FAMILY:
381411
wr_rd(ECP3_LSCC_REFRESH, NULL, 0, NULL, 0);
@@ -398,7 +428,11 @@ bool Lattice::program_mem()
398428
printSuccess("DONE");
399429
}
400430

401-
if (was_refreshed) {
431+
if (_fpga_family == NEXUS_FAMILY) {
432+
wr_rd(REFRESH, NULL, 0, NULL, 0);
433+
_jtag->set_state(Jtag::RUN_TEST_IDLE);
434+
_jtag->toggleClk(2);
435+
402436
/* LSC_DEVICE_CONTROL 0x7D -- configuration reset */
403437
printInfo("Configuration Logic Reset: ", false);
404438
uint8_t tx_tmp[1] = {0x08};
@@ -442,6 +476,17 @@ bool Lattice::program_mem()
442476
printSuccess("DONE");
443477
}
444478

479+
if (_fpga_family == NEXUS_FAMILY) {
480+
printInfo("SRAM erase check: ", false);
481+
uint64_t status = readStatusReg();
482+
if ((status & 0x000000000002100) != 0) {
483+
printError("FAIL");
484+
return false;
485+
} else {
486+
printSuccess("DONE");
487+
}
488+
}
489+
445490
/* LSC_INIT_ADDRESS */
446491
if (_fpga_family == ECP3_FAMILY) {
447492
wr_rd(ECP3_RESET_ADDRESS, NULL, 0, NULL, 0);
@@ -460,7 +505,7 @@ bool Lattice::program_mem()
460505
return false;
461506
}
462507
} else {
463-
wr_rd(0x46, NULL, 0, NULL, 0);
508+
wr_rd(RESET_CFG_ADDR, NULL, 0, NULL, 0); // LSC_INIT_ADDRESS
464509
_jtag->set_state(Jtag::RUN_TEST_IDLE);
465510
_jtag->toggleClk(1000);
466511
}
@@ -476,7 +521,7 @@ bool Lattice::program_mem()
476521

477522
wr_rd(ECP3_LSCC_BITSTREAM_BURST, NULL, 0, NULL, 0);
478523
} else {
479-
wr_rd(0x7A, NULL, 0, NULL, 0);
524+
wr_rd(LSC_BITSTREAM_BURST, NULL, 0, NULL, 0);
480525
_jtag->set_state(Jtag::RUN_TEST_IDLE);
481526
_jtag->toggleClk(2);
482527
}
@@ -521,12 +566,18 @@ bool Lattice::program_mem()
521566
_jtag->toggleClk(1000);
522567

523568
uint32_t status_mask;
569+
uint32_t status_val = 0;
524570
if (_fpga_family == MACHXO3D_FAMILY)
525571
status_mask = REG_STATUS_MACHXO3D_CNF_CHK_MASK;
572+
else if (_fpga_family == NEXUS_FAMILY) {
573+
status_val = REG_STATUS_DONE;
574+
status_mask = REG_STATUS_DONE | REG_STATUS_BUSY | REG_STATUS_FAIL
575+
| REG_NEXUS_STATUS_BSE_ERR_MASK;
576+
}
526577
else
527578
status_mask = REG_STATUS_CNF_CHK_MASK;
528579

529-
if (checkStatus(0, status_mask)) {
580+
if (checkStatus(status_val, status_mask)) {
530581
progress.done();
531582
} else {
532583
progress.fail();
@@ -577,6 +628,11 @@ bool Lattice::program_mem()
577628

578629
/* bypass */
579630
wr_rd(0xff, NULL, 0, NULL, 0);
631+
if (_fpga_family == NEXUS_FAMILY) {
632+
_jtag->set_state(Jtag::RUN_TEST_IDLE);
633+
_jtag->toggleClk(100);
634+
usleep_ecp3(1000000);
635+
}
580636
_jtag->go_test_logic_reset();
581637
return true;
582638
}
@@ -1036,9 +1092,6 @@ bool Lattice::EnableISC(uint8_t flash_mode)
10361092
_jtag->toggleClk(5, 1);
10371093
usleep_ecp3(20000); // 0.20s
10381094
return true;
1039-
} else if (_fpga_family == NEXUS_FAMILY) {
1040-
cmd = (_mode == FLASH_MODE) ? ISC_ENABLE: ISC_ENABLE_X;
1041-
flash_mode = 0;
10421095
}
10431096

10441097
wr_rd(cmd, &flash_mode, 1, NULL, 0);
@@ -1516,7 +1569,12 @@ bool Lattice::flashErase(uint32_t mask)
15161569
wr_rd(FLASH_ERASE, tx, 1, NULL, 0);
15171570
}
15181571
_jtag->set_state(Jtag::RUN_TEST_IDLE);
1519-
_jtag->toggleClk(1000);
1572+
if (_fpga_family == NEXUS_FAMILY) {
1573+
_jtag->toggleClk(100);
1574+
usleep_ecp3(1000000);
1575+
} else {
1576+
_jtag->toggleClk(1000);
1577+
}
15201578

15211579
if (!pollBusyFlag())
15221580
return false;

‎src/lattice.hpp‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -110,6 +110,7 @@ class Lattice: public Device, SPIInterface {
110110
* \brief erase SRAM
111111
*/
112112
bool clearSRAM();
113+
bool preload();
113114
void unlock();
114115
bool EnableISC(uint8_t flash_mode);
115116
bool DisableISC();

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