Skip to content

Commit 4a17129

Browse files
trabucayretrabucayre
committed
spiOverJtag: reworks Artix and Spartan 7 approach:
 For a specific FPGA size, pins name is only a matter of package, internally physical pads are the same: a unique bitstream per size is necessary. - a dict is added with supported packages per size - only one bitstream is produces for artix/spartan7 size, package+size bitstreams are only symlinks. - constraints files are also updated with BSCANE2/DRCK clocks constraints - the gz is produces by build.py instead of by the Makefile - all possibles bitstreams for XC7A/XC7S are now present.
1 parent 9c86c53 commit 4a17129

File tree

87 files changed

+164
-68
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

87 files changed

+164
-68
lines changed

‎spiOverJtag/Makefile‎

Lines changed: 4 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -3,13 +3,8 @@ XILINX_PARTS := xc3s500evq100 \
33
xc6slx16ftg256 xc6slx16csg324 xc6slx25csg324 xc6slx45csg324 xc6slx100fgg484 \
44
xc6slx25tcsg324 xc6slx45tfgg484 xc6slx150tfgg484 xc6slx150tcsg484 \
55
xc6vlx130tff784 \
6-
xc7a15tcpg236 xc7a15tfgg484 \
7-
xc7a25tcpg238 xc7a25tcsg325 \
8-
xc7a35tcpg236 xc7a35tcsg324 xc7a35tftg256 xc7a35tfgg484 \
9-
xc7a50tcsg324 xc7a50tfgg484 xc7a50tcpg236 xc7a50tcsg325 xc7a75tfgg484 \
10-
xc7a100tcsg324 xc7a100tfgg484 xc7a100tfgg676\
11-
xc7a200tsbg484 xc7a200tfbg484 xc7a200tfbg676\
12-
xc7s6ftgb196 xc7s25csga225 xc7s25csga324 xc7s50csga324 \
6+
xc7a12t xc7a15t xc7a25t xc7a35t xc7a50t xc7a75t xc7a100t xc7a200t \
7+
xc7s6 xc7s15 xc7s25 xc7s50 xc7s75 xc7s100 \
138
xc7k70tfbg484 xc7k70tfbg676 \
149
xc7k160tffg676 \
1510
xc7k325tffg676 xc7k325tffg900 \
@@ -19,7 +14,7 @@ XILINX_PARTS := xc3s500evq100 \
1914
xcku040-ffva1156 xcku060-ffva1156 \
2015
xcku5p-ffvb676 \
2116
xcvu9p-flga2104 xcvu37p-fsvh2892 \
22-
xcau15p-ffvb676
17+
xcau15p-ffvb676
2318
XILINX_BIT_FILES := $(addsuffix .bit.gz,$(addprefix spiOverJtag_, $(XILINX_PARTS)))
2419

2520
ALTERA_PARTS := 10cl025256 10cl016484 10cl055484 \
@@ -39,7 +34,7 @@ tmp_efinix_%/efinix_spiOverJtag.bit : efinix_spiOverJtag.v
3934
./efinix_build.py --device $*
4035

4136
$(XILINX_BIT_FILES) : spiOverJtag_%.bit.gz : tmp_%/spiOverJtag.bit
42-
gzip -9 -c $< > $@
37+
4338
tmp_%/spiOverJtag.bit : xilinx_spiOverJtag.v spiOverJtag_core.v
4439
./build.py $*
4540

‎spiOverJtag/build.py‎

Lines changed: 56 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,30 @@
11
#!/usr/bin/env python3
2-
from edalize.edatool import get_edatool
2+
33
import os
44

5+
from edalize.edatool import get_edatool
6+
7+
packages = {
8+
"Artix": {
9+
"xc7a12t" : ["cpg238", "csg325"],
10+
"xc7a15t" : ["cpg236", "csg324", "csg325", "ftg256", "fgg484"],
11+
"xc7a25t" : ["cpg238", "csg325"],
12+
"xc7a35t" : ["cpg236", "csg324", "csg325", "ftg256", "fgg484"],
13+
"xc7a50t" : ["cpg236", "csg324", "csg325", "ftg256", "fgg484"],
14+
"xc7a75t" : ["csg324", "ftg256", "fgg484", "fgg676"],
15+
"xc7a100t" : ["csg324", "ftg256", "fgg484", "fgg676"],
16+
"xc7a200t" : ["sbg484", "fbg484", "fbg676", "ffg1156"],
17+
},
18+
"Spartan 7": {
19+
"xc7s6" : ["ftgb196", "cpga196", "csga225"],
20+
"xc7s15" : ["ftgb196", "cpga196", "csga225"],
21+
"xc7s25" : ["ftgb196", "csga225", "csga324"],
22+
"xc7s50" : ["ftgb196", "csga324", "fgga484"],
23+
"xc7s75" : ["fgga484", "fgga676"],
24+
"xc7s100" : ["fgga484", "fgga676"],
25+
},
26+
}
27+
528
if len(os.sys.argv) != 2:
629
print("missing board param")
730
os.sys.exit()
@@ -16,9 +39,10 @@
1639
else:
1740
print ("Successfully created the directory %s " % build_dir)
1841

19-
currDir = os.path.abspath(os.path.curdir) + '/'
20-
files = []
42+
currDir = os.path.abspath(os.path.curdir) + '/'
43+
files = []
2144
parameters = {}
45+
pkg_name = None
2246

2347
subpart = part[0:4].lower()
2448
if subpart == '10cl':
@@ -39,7 +63,8 @@
3963
'file_type': 'tclSource'})
4064
elif subpart == "xc7a":
4165
family = "Artix"
42-
tool = "vivado"
66+
tool = "vivado"
67+
model = subpart
4368
elif subpart == "xc7v":
4469
family = "Virtex 7"
4570
tool = "vivado"
@@ -54,7 +79,8 @@
5479
speed = -2
5580
elif subpart == "xc7s":
5681
family = "Spartan 7"
57-
tool = "vivado"
82+
tool = "vivado"
83+
model = subpart
5884
elif subpart == "xc6s":
5985
family = "Spartan6"
6086
tool = "ise"
@@ -74,6 +100,10 @@
74100
print("Error: unknown device")
75101
os.sys.exit()
76102

103+
if model in ["xc7a", "xc7s"]:
104+
pkg = packages[family][part][0]
105+
pkg_name = f"{model}_{pkg}"
106+
77107
if tool in ["ise", "vivado"]:
78108
pkg_name = {
79109
"xc3s500evq100" : "xc3s_vq100",
@@ -89,45 +119,21 @@
89119
"xc6slx150tcsg484" : "xc6s_csg484",
90120
"xc6slx150tfgg484" : "xc6s_t_fgg484",
91121
"xc6vlx130tff784" : "xc6v_ff784",
92-
"xc7a15tcpg236" : "xc7a_cpg236",
93-
"xc7a15tfgg484" : "xc7a_fgg484",
94-
"xc7a25tcpg238" : "xc7a_cpg238",
95-
"xc7a25tcsg325" : "xc7a_csg325",
96-
"xc7a35tcpg236" : "xc7a_cpg236",
97-
"xc7a35tcsg324" : "xc7a_csg324",
98-
"xc7a35tftg256" : "xc7a_ftg256",
99-
"xc7a35tfgg484" : "xc7a_fgg484",
100-
"xc7a50tcpg236" : "xc7a_cpg236",
101-
"xc7a50tcsg324" : "xc7a_csg324",
102-
"xc7a50tfgg484" : "xc7a_fgg484",
103-
"xc7a50tcsg325" : "xc7a_csg325",
104-
"xc7a75tfgg484" : "xc7a_fgg484",
105-
"xc7a100tcsg324" : "xc7a_csg324",
106-
"xc7a100tfgg484" : "xc7a_fgg484",
107-
"xc7a100tfgg676" : "xc7a_fgg676",
108-
"xc7a200tsbg484" : "xc7a_sbg484",
109-
"xc7a200tfbg484" : "xc7a_fbg484",
110-
"xc7a200tfbg676" : "xc7a_fbg676",
111122
"xc7k70tfbg484" : "xc7k_fbg484",
112123
"xc7k70tfbg676" : "xc7k_fbg676",
113124
"xc7k160tffg676" : "xc7k_ffg676",
114125
"xc7k325tffg676" : "xc7k_ffg676",
115126
"xc7k325tffg900" : "xc7k_ffg900",
116127
"xc7k420tffg901" : "xc7k_ffg901",
117128
"xc7vx330tffg1157" : "xc7v_ffg1157",
118-
"xc7s6ftgb196" : "xc7s_ftgb196",
119-
"xc7s25csga225" : "xc7s_csga225",
120-
"xc7s25csga324" : "xc7s_csga324",
121-
"xc7s50csga324" : "xc7s_csga324",
122-
"xc7s75fgga676" : "xc7s_fgga676",
123129
"xcku040-ffva1156" : "xcku040_ffva1156",
124130
"xcku060-ffva1156" : "xcku060_ffva1156",
125131
"xcvu9p-flga2104" : "xcvu9p_flga2104",
126132
"xcvu37p-fsvh2892" : "xcvu37p_fsvh2892",
127133
"xcku3p-ffva676" : "xcku3p_ffva676",
128134
"xcku5p-ffvb676" : "xcku5p_ffvb676",
129135
"xcau15p-ffvb676" : "xcau15p_ffvb676",
130-
}[part]
136+
}.get(part, pkg_name)
131137
if tool == "ise":
132138
cst_type = "UCF"
133139
tool_options = {'family': family,
@@ -171,7 +177,10 @@
171177
}
172178
else:
173179
cst_type = "xdc"
174-
if family == "Xilinx UltraScale":
180+
# Artix/Spartan 7 Specific use case:
181+
if family in ["Artix", "Spartan 7"]:
182+
tool_options = {'part': f"{part}{pkg}-1"}
183+
elif family == "Xilinx UltraScale":
175184
if part in ["xcvu9p-flga2104", "xcku5p-ffvb676"]:
176185
tool_options = {'part': part + '-1-e'}
177186
parameters["secondaryflash"]= {
@@ -194,6 +203,7 @@
194203
tool_options = {'part': part + '-2-e'}
195204
else:
196205
tool_options = {'part': part + '-1'}
206+
197207
cst_file = currDir + "constr_" + pkg_name + "." + cst_type.lower()
198208
files.append({'name': currDir + 'xilinx_spiOverJtag.v',
199209
'file_type': 'verilogSource'})
@@ -245,5 +255,18 @@
245255

246256
if tool == "vivado":
247257
import shutil
248-
shutil.copy("tmp_" + part + "/spiOverJtag.runs/impl_1/spiOverJtag.bit",
249-
"tmp_" + part);
258+
import subprocess
259+
import gzip
260+
261+
# Compress bitstream.
262+
with open(f"tmp_{part}/spiOverJtag.bit", 'rb') as bit:
263+
with gzip.open(f"spiOverJtag_{part}.bit.gz", 'wb', compresslevel=9) as bit_gz:
264+
shutil.copyfileobj(bit, bit_gz)
265+
266+
# Create Symbolic links for all supported packages.
267+
if family in ["Artix", "Spartan 7"]:
268+
in_file = f"spiOverJtag_{part}.bit.gz"
269+
for pkg in packages[family][part]:
270+
out_file = f"spiOverJtag_{part}{pkg}.bit.gz"
271+
if not os.path.exists(out_file):
272+
subprocess.run(["ln", "-s", in_file, out_file])

‎spiOverJtag/constr_xc7a_cpg236.xdc‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,9 +2,12 @@ set_property CFGBVS VCCO [current_design]
22
set_property CONFIG_VOLTAGE 3.3 [current_design]
33
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
44
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
5+
56
set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS33} [get_ports {csn}];
67
set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}];
78
set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}];
89
set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}];
910
set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}];
1011

12+
create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK}]
13+
create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK}]

‎spiOverJtag/constr_xc7a_cpg238.xdc‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,3 +9,5 @@ set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}];
99
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}];
1010
set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}];
1111

12+
create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK}]
13+
create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK}]

‎spiOverJtag/constr_xc7a_csg324.xdc‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,3 +8,6 @@ set_property -dict {PACKAGE_PIN K17 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}];
88
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}];
99
set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}];
1010
set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}];
11+
12+
create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK}]
13+
create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK}]

‎spiOverJtag/constr_xc7a_csg325.xdc‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,3 +9,5 @@ set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}];
99
set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}];
1010
set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}];
1111

12+
create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK]}}
13+
create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK]}}

‎spiOverJtag/constr_xc7a_csg325_1v35.xdc‎

Lines changed: 24 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -1,23 +1,24 @@
1-
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
2-
set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design]
3-
4-
set_property CONFIG_VOLTAGE 1.8 [current_design]
5-
set_property CFGBVS GND [current_design]
6-
7-
set_property CONFIG_MODE SPIx4 [current_design]
8-
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR NO [current_design]
9-
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
10-
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
11-
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
12-
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]
13-
14-
set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]
15-
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDOWN [current_design]
16-
set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN ENABLE [current_design]
17-
18-
set_property -dict {PACKAGE_PIN L15 IOSTANDARD SSTL135_R} [get_ports csn]
19-
set_property -dict {PACKAGE_PIN K16 IOSTANDARD SSTL135_R} [get_ports sdi_dq0]
20-
set_property -dict {PACKAGE_PIN L17 IOSTANDARD SSTL135_R} [get_ports sdo_dq1]
21-
set_property -dict {PACKAGE_PIN J15 IOSTANDARD SSTL135_R} [get_ports wpn_dq2]
22-
set_property -dict {PACKAGE_PIN J16 IOSTANDARD SSTL135_R} [get_ports hldn_dq3]
23-
1+
set_property CFGBVS GND [current_design]
2+
set_property CONFIG_VOLTAGE 1.8 [current_design]
3+
set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design]
4+
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
5+
6+
set_property CONFIG_MODE SPIx4 [current_design]
7+
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR NO [current_design]
8+
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
9+
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
10+
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
11+
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]
12+
13+
set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]
14+
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDOWN [current_design]
15+
set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN ENABLE [current_design]
16+
17+
set_property -dict {PACKAGE_PIN L15 IOSTANDARD SSTL135_R} [get_ports csn]
18+
set_property -dict {PACKAGE_PIN K16 IOSTANDARD SSTL135_R} [get_ports sdi_dq0]
19+
set_property -dict {PACKAGE_PIN L17 IOSTANDARD SSTL135_R} [get_ports sdo_dq1]
20+
set_property -dict {PACKAGE_PIN J15 IOSTANDARD SSTL135_R} [get_ports wpn_dq2]
21+
set_property -dict {PACKAGE_PIN J16 IOSTANDARD SSTL135_R} [get_ports hldn_dq3]
22+
23+
create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK]}}
24+
create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK]}}

‎spiOverJtag/constr_xc7a_fbg484.xdc‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,3 +9,5 @@ set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVTTL} [get_ports {sdo_dq1}]
99
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVTTL} [get_ports {wpn_dq2}]
1010
set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVTTL} [get_ports {hldn_dq3}]
1111

12+
create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK}]
13+
create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK}]

‎spiOverJtag/constr_xc7a_fbg676.xdc‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,3 +8,6 @@ set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVTTL} [get_ports {sdi_dq0}]
88
set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVTTL} [get_ports {sdo_dq1}]
99
set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVTTL} [get_ports {wpn_dq2}]
1010
set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVTTL} [get_ports {hldn_dq3}]
11+
12+
create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK}]
13+
create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK}]

‎spiOverJtag/constr_xc7a_fgg484.xdc‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,13 @@
11
set_property CFGBVS VCCO [current_design]
22
set_property CONFIG_VOLTAGE 3.3 [current_design]
33
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
4+
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
45

56
set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVTTL} [get_ports {csn}]
67
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVTTL} [get_ports {sdi_dq0}]
78
set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVTTL} [get_ports {sdo_dq1}]
89
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVTTL} [get_ports {wpn_dq2}]
910
set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVTTL} [get_ports {hldn_dq3}]
1011

12+
create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK}]
13+
create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK}]

0 commit comments

Comments
 (0)