spiOverJtag: added xc7a75tfgg676 variant

Author: Gwenhael Goavec-Merou

spiOverJtag/Makefile

@@ -6,7 +6,8 @@ XILINX_PARTS := xc3s500evq100 \
 	xc7a15tcpg236 xc7a15tfgg484 \
 	xc7a25tcpg238 xc7a25tcsg325 \
 	xc7a35tcpg236 xc7a35tcsg324 xc7a35tftg256 xc7a35tfgg484 \
-	xc7a50tcsg324 xc7a50tfgg484 xc7a50tcpg236 xc7a50tcsg325 xc7a75tfgg484 \
+	xc7a50tcsg324 xc7a50tfgg484 xc7a50tcpg236 xc7a50tcsg325 \
+	xc7a75tfgg484 xc7a75tfgg676 \
 	xc7a100tcsg324 xc7a100tfgg484 xc7a100tfgg676\
 	xc7a200tsbg484 xc7a200tfbg484 xc7a200tfbg676\
 	xc7s6ftgb196 xc7s25csga225 xc7s25csga324 xc7s50csga324 \

spiOverJtag/build.py

@@ -102,6 +102,7 @@
         "xc7a50tfgg484"    : "xc7a_fgg484",
         "xc7a50tcsg325"    : "xc7a_csg325",
         "xc7a75tfgg484"    : "xc7a_fgg484",
+        "xc7a75tfgg676"    : "xc7a_fgg676",
         "xc7a100tcsg324"   : "xc7a_csg324",
         "xc7a100tfgg484"   : "xc7a_fgg484",
         "xc7a100tfgg676"   : "xc7a_fgg676",

spiOverJtag/constr_xc7a_fgg676.xdc

@@ -3,9 +3,10 @@ set_property CONFIG_VOLTAGE 3.3 [current_design]
 set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
 set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
 
-set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVTTL} [get_ports {csn}]
+set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVTTL} [get_ports {csn}]
 set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVTTL} [get_ports {sdi_dq0}]
 set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVTTL} [get_ports {sdo_dq1}]
 set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVTTL} [get_ports {wpn_dq2}]
-set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVTTL} [get_ports {hldn_dq3}]
+set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVTTL} [get_ports {hldn_dq3}]
 
+create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins bscane2_inst/DRCK]}