lattice: fixed ECP3 support: now working

Author: trabucayre

src/lattice.cpp

@@ -12,7 +12,9 @@
 #include <string.h>
 #include <unistd.h>
 
+#include <iomanip>
 #include <iostream>
+#include <list>
 #include <stdexcept>
 
 #include "jtag.hpp"
@@ -280,9 +282,17 @@ bool Lattice::checkStatus(uint64_t val, uint64_t mask)
 	return ((reg & mask) == val) ? true : false;
 }
 
+void Lattice::usleep_ecp3(uint64_t us_time)
+{
+	const uint32_t clk_period = 1e9/static_cast<float>(_jtag->getClkFreq());
+	const uint32_t clk_len = (us_time * 1000) / clk_period;
+	_jtag->toggleClk((us_time * 1000) / clk_period, 0); // 0.5s
+}
+
 bool Lattice::program_mem()
 {
 	bool err;
+
 	LatticeBitParser _bit(_filename, false, _verbose);
 
 	printInfo("Open file: ", false);
@@ -376,8 +386,8 @@ bool Lattice::program_mem()
 		case ECP3_FAMILY:
 			wr_rd(ECP3_LSCC_REFRESH, NULL, 0, NULL, 0);
 			_jtag->set_state(Jtag::RUN_TEST_IDLE);
-			_jtag->toggleClk(5e8 / clk_period); // 0.5s
-			displayReadReg(readStatusReg());
+			_jtag->toggleClk(5, 1);
+			usleep_ecp3(500000);  // 0.5s
 			was_refreshed = false;
 			break;
 		default:
@@ -431,7 +441,9 @@ bool Lattice::program_mem()
 		uint32_t dummy = 0xffffffff;
 		wr_rd(ECP3_ISC_PROGRAM_USERCODE, (uint8_t *)&dummy, 4, NULL, 0);
 		_jtag->set_state(Jtag::RUN_TEST_IDLE);
-		_jtag->toggleClk(2e6 / clk_period); // 2ms
+		_jtag->toggleClk(5, 1);
+		usleep_ecp3(2000); // 2ms
+
 		uint32_t rx = 0;
 		wr_rd(ECP3_READ_USERCODE, (uint8_t *)&dummy, 4, (uint8_t *)&rx, 4);
 		if (rx != 0xffffffff) {
@@ -462,8 +474,10 @@ bool Lattice::program_mem()
 	if (_fpga_family == ECP3_FAMILY) {
 		wr_rd(ECP3_RESET_ADDRESS, NULL, 0, NULL, 0);
 		_jtag->set_state(Jtag::RUN_TEST_IDLE);
-		_jtag->toggleClk(2e6 / clk_period); // 2ms
-		/* read user code */
+		_jtag->toggleClk(5);
+		usleep_ecp3(2000); // 2ms
+
+		/* read user code (User Code register must have all bit set cleared) */
 		const uint32_t dummy = 0xffffffff;
 		uint32_t rx = 0;
 		wr_rd(ECP3_READ_USERCODE, (uint8_t *)&dummy, 4, (uint8_t *)&rx, 4);
@@ -482,6 +496,12 @@ bool Lattice::program_mem()
 	const uint8_t *data = _bit.getData();
 	int length = _bit.getLength()/8;
 	if (_fpga_family == ECP3_FAMILY) {
+		/* Reset Address */
+		wr_rd(ECP3_RESET_ADDRESS, NULL, 0, NULL, 0);
+		_jtag->set_state(Jtag::RUN_TEST_IDLE);
+		_jtag->toggleClk(5, 1);
+		usleep_ecp3(2000); // 2ms
+
 		wr_rd(ECP3_LSCC_BITSTREAM_BURST, NULL, 0, NULL, 0);
 	} else {
 		wr_rd(0x7A, NULL, 0, NULL, 0);
@@ -510,51 +530,47 @@ bool Lattice::program_mem()
 	}
 
 	_jtag->set_state(Jtag::RUN_TEST_IDLE);
+
 	if (_fpga_family == ECP3_FAMILY) {
-		_jtag->toggleClk(200e6 / clk_period); // 200ms
-		/* Verify USERCODE */
-		uint8_t r[] = {0xff, 0xff, 0xff, 0xff};
-		uint8_t t[4];
-		wr_rd(0x17, r, 4, t, 4);
-		printf("%02x %02x %02x %02x\n", t[0], t[1], t[2], t[3]);
-		// isc disable
-		wr_rd(0x1e, NULL, 0, NULL, 0);
-		_jtag->set_state(Jtag::RUN_TEST_IDLE);
-		_jtag->toggleClk(5);
-		// bypass
-		wr_rd(0xff, NULL, 0, NULL, 0);
-		_jtag->set_state(Jtag::RUN_TEST_IDLE);
-		_jtag->toggleClk(100);
-		// Verify STATUS Register
-		uint64_t status = readStatusReg();
-		printf("status %08x %08x\n", status, status & 0x60007);
-		displayReadReg(status);
-		return true;
+		_jtag->toggleClk(256, 1);
+		usleep_ecp3(2000);
+
+		/* Verifiy User Code register */
+		uint32_t rx = 0;
+		uint8_t dummy[] = {0xff, 0xff, 0xff, 0xff};
+		wr_rd(ECP3_READ_USERCODE, dummy, 4, (uint8_t *)&rx, 4);
+		if (rx != 0x00000000) {
+			char message[256];
+			snprintf(message, 256, "failed: 0x%08x instead of 0x00000000", rx);
+			printError(message);
+			return false;
+		}
 	} else {
 		_jtag->toggleClk(1000);
 	}
 
-	uint32_t status_mask;
-	if (_fpga_family == MACHXO3D_FAMILY)
-		status_mask = REG_STATUS_MACHXO3D_CNF_CHK_MASK;
-	else
-		status_mask = REG_STATUS_CNF_CHK_MASK;
+	if (_fpga_family != ECP3_FAMILY) {
+		uint32_t status_mask;
+		if (_fpga_family == MACHXO3D_FAMILY)
+			status_mask = REG_STATUS_MACHXO3D_CNF_CHK_MASK;
+		else
+			status_mask = REG_STATUS_CNF_CHK_MASK;
 
-	if (checkStatus(0, status_mask)) {
-		progress.done();
-	} else {
-		progress.fail();
-		displayReadReg(readStatusReg());
-		return false;
-	}
+		if (checkStatus(0, status_mask)) {
+			progress.done();
+		} else {
+			progress.fail();
+			displayReadReg(readStatusReg());
+			return false;
+		}
 
-	wr_rd(0xff, NULL, 0, NULL, 0);
+		/* bypass */
+		wr_rd(0xff, NULL, 0, NULL, 0);
+	}
 
-	if (_verbose)
+	if (_verbose && _fpga_family != ECP3_FAMILY)
 		printf("userCode: %08x\n", userCode());
 
-	/* bypass */
-	wr_rd(0xff, NULL, 0, NULL, 0);
 	/* disable configuration mode */
 	printInfo("Disable configuration: ", false);
 	if (!DisableISC()) {
@@ -565,11 +581,23 @@ bool Lattice::program_mem()
 		printSuccess("DONE");
 	}
 
+	if (_fpga_family == ECP3_FAMILY) {
+		/* Bypass */
+		wr_rd(0xff, NULL, 0, NULL, 0);
+		_jtag->set_state(Jtag::RUN_TEST_IDLE);
+		_jtag->toggleClk(100, 1);
+		usleep_ecp3(1000);
+
+		// Verify STATUS Register
+		uint64_t status = readStatusReg();
+		printf("status %08x %08x\n", status, status & 0x60007);
+		displayReadReg(status);
+		_jtag->toggleClk(5, 1);
+	}
+
 	if (_verbose)
 		displayReadReg(readStatusReg());
 
-	/* bypass */
-	wr_rd(0xff, NULL, 0, NULL, 0);
 	_jtag->go_test_logic_reset();
 	return true;
 }
@@ -989,11 +1017,10 @@ void Lattice::program(unsigned int offset, bool unprotect_flash)
 bool Lattice::EnableISC(uint8_t flash_mode)
 {
 	if (_fpga_family == ECP3_FAMILY) {
-		const uint32_t clk_period = 1e9/static_cast<float>(_jtag->getClkFreq());
-		const uint32_t clk_len = 2e7 / clk_period;
 		wr_rd(ECP3_ISC_ENABLE, NULL, 0, NULL, 0);
 		_jtag->set_state(Jtag::RUN_TEST_IDLE);
-		_jtag->toggleClk(clk_len);
+		_jtag->toggleClk(5, 1); // 0.5s
+		usleep_ecp3(20000); // 0.20s
 		return true;
 	}
 
@@ -1010,6 +1037,13 @@ bool Lattice::EnableISC(uint8_t flash_mode)
 
 bool Lattice::DisableISC()
 {
+	if (_fpga_family == ECP3_FAMILY) {
+		/** Shift in ISC DISABLE instruction */
+		_jtag->shiftIR(0x1E, 8, Jtag::RUN_TEST_IDLE);
+		_jtag->toggleClk(5, 1);
+		usleep_ecp3(200000);
+		return true;
+	}
 	wr_rd(ISC_DISABLE, NULL, 0, NULL, 0);
 	_jtag->set_state(Jtag::RUN_TEST_IDLE);
 	_jtag->toggleClk(1000);
@@ -1153,8 +1187,75 @@ bool Lattice::wr_rd(uint8_t cmd,
 	return true;
 }
 
+typedef struct {
+	std::string description;
+	uint8_t offset;
+	uint8_t size;
+	std::map<int, std::string> reg_cnt;
+} reg_struct_t;
+
+#define REG_ENTRY(_description, _offset, _size, ...) \
+	{_description, _offset, _size, {__VA_ARGS__}}
+
+static const std::map<std::string, std::list<reg_struct_t>> reg_content = {
+	{"StatusRegister", std::list<reg_struct_t>{
+		REG_ENTRY("CRC Error",            0, 1, {0, "OK"}, {1, "KO"}),
+		REG_ENTRY("ID Verify failed",     1, 1, {0, "No"}, {1, "Yes"}),
+		REG_ENTRY("Invalid Command",      2, 1, {0, "No"}, {1, "Yes"}),
+		REG_ENTRY("SPIm Mode Error",      3, 1, {0, "No"}, {1, "Yes"}),
+		REG_ENTRY("Device locked",        4, 1, {0, "No"}, {1, "Yes"}),
+		REG_ENTRY("Key Fire",             5, 1, {0, "No"}, {1, "Yes"}),
+		REG_ENTRY("Alignement Preamble",  6, 1, {0, "No"}, {1, "Yes"}),
+		REG_ENTRY("Encryption Preamble",  7, 1, {0, "No"}, {1, "Yes"}),
+		REG_ENTRY("Std Preamble",         8, 1, {0, "No"}, {1, "Yes"}),
+		REG_ENTRY("HFC",                  9, 1, {0, "No"}, {1, "Yes"}),
+		REG_ENTRY("Memory Cleared",      15, 1, {0, "No"}, {1, "Yes"}),
+		REG_ENTRY("Device Secured",      16, 1, {0, "No"}, {1, "Yes"}),
+		REG_ENTRY("Device Configured",   17, 1, {0, "No"}, {1, "Yes"}),
+		REG_ENTRY("Non-JTAG Mode",       18, 1, {0, "No"}, {1, "Yes"}),
+		REG_ENTRY("ReadBack Mode",       19, 1, {0, "No"}, {1, "Yes"}),
+		REG_ENTRY("Bypass Mode",         20, 1, {0, "No"}, {1, "Yes"}),
+		REG_ENTRY("Flow Trough",         21, 1, {0, "No"}, {1, "Yes"}),
+		REG_ENTRY("Configuration Mode",  22, 1, {0, "No"}, {1, "Yes"}),
+		REG_ENTRY("Transparent Mode",    23, 1, {0, "No"}, {1, "Yes"}),
+	}},
+};
+
 void Lattice::displayReadReg(uint64_t dev)
 {
+	if (_fpga_family == ECP3_FAMILY) {
+		auto reg = reg_content.find("StatusRegister");
+		if (reg == reg_content.end()) {
+			printError("Unknown register StatusRegister");
+			return;
+		}
+
+		std::stringstream raw_val;
+		raw_val << "0x" << std::hex << dev;
+		printSuccess("Register raw value: " + raw_val.str());
+
+		const std::list<reg_struct_t> regs = reg->second;
+		for (reg_struct_t r: regs) {
+			uint8_t offset = r.offset;
+			uint8_t size = r.size;
+			uint32_t mask = (1 << size) - 1;
+			uint32_t val = (dev >> offset) & mask;
+			std::stringstream ss, desc;
+			desc << r.description;
+			ss << std::setw(20) << std::left << r.description;
+			if (r.reg_cnt.size() != 0) {
+				ss << r.reg_cnt[val];
+			} else {
+				std::stringstream hex_val;
+				hex_val << "0x" << std::hex << val;
+				ss << hex_val.str();
+			}
+
+			printInfo(ss.str());
+		}
+		return;
+	}
+
 	uint8_t err;
 	printf("displayReadReg\n");
 	if (dev & 1<<0) printf("\tTRAN Mode\n");
@@ -1349,11 +1450,10 @@ bool Lattice::flashErase(uint32_t  mask)
 		};
 		wr_rd(FLASH_ERASE, tx, 2, NULL, 0);
 	} else if (_fpga_family == ECP3_FAMILY) {
-		const uint32_t clk_period = 1e9/static_cast<float>(_jtag->getClkFreq());
-		const uint32_t clk_len = 2e7 / clk_period;
 		wr_rd(ECP3_ISC_ERASE, NULL, 0, NULL, 0);
 		_jtag->set_state(Jtag::RUN_TEST_IDLE);
-		_jtag->toggleClk(clk_len);
+		_jtag->toggleClk(5, 1);
+		usleep_ecp3(2000000);  // 2s
 		return true;
 	} else {
 		uint8_t tx[1] = {(uint8_t)(mask & 0xff)};

src/lattice.hpp

@@ -123,6 +123,9 @@ class Lattice: public Device, SPIInterface {
 		/* test */
 		bool checkID();
 
+		/************************* MODS for ECP3 ******************************/
+		void usleep_ecp3(uint64_t us_time);
+
 		/*********************** MODS FOR MacXO3D *****************************/
 		enum lattice_flash_sector_t {
 			LATTICE_FLASH_UNDEFINED = 0,