Failure to create a spiOverJtag bitstream for some Xilinx devices

[pkuzmin]

For xc3s500evq100 we get an error

ERROR:HDLCompilers:27 - "../xilinx_spiOverJtag.v" line 133 Illegal redeclaration of 'tdo'

For xc6vlx130tff784 we get errors

ERROR:NgdBuild:604 - logical block 'bscane2_inst' with type 'BSCANE2' could not
   be resolved. A pin name misspelling can cause this, a missing edif or ngc
   file, case mismatch between the block name and the edif or ngc file name, or
   the misspelling of a type name. Symbol 'BSCANE2' is not supported in target
   'virtex6'.

For xcku3p-ffva676, xcku5p-ffvb676, xcku040-ffva1156, xcvu9p-flga2104, xcau15p-ffvb676

ERROR: [Synth 8-36] 'csn' is not declared [/.../openFPGALoader/spiOverJtag/xilinx_spiOverJtag.v:55]
ERROR: [Synth 8-36] 'sdi_dq0' is not declared [/.../openFPGALoader/spiOverJtag/xilinx_spiOverJtag.v:57]
ERROR: [Synth 8-36] 'sdo_dq1' is not declared [/.../openFPGALoader/spiOverJtag/xilinx_spiOverJtag.v:58]
ERROR: [Synth 8-36] 'wpn_dq2' is not declared [/.../openFPGALoader/spiOverJtag/xilinx_spiOverJtag.v:59]
ERROR: [Synth 8-36] 'hldn_dq3' is not declared [/.../openFPGALoader/spiOverJtag/xilinx_spiOverJtag.v:60]
ERROR: [Synth 8-36] 'sdo_dq1' is not declared [/.../openFPGALoader/spiOverJtag/xilinx_spiOverJtag.v:73]
ERROR: [Synth 8-36] 'hldn_dq3' is not declared [/.../openFPGALoader/spiOverJtag/xilinx_spiOverJtag.v:74]
ERROR: [Synth 8-36] 'wpn_dq2' is not declared [/.../openFPGALoader/spiOverJtag/xilinx_spiOverJtag.v:74]
ERROR: [Synth 8-36] 'sdi_dq0' is not declared [/.../openFPGALoader/spiOverJtag/xilinx_spiOverJtag.v:74]
ERROR: [Synth 8-36] 'csn' is not declared [/.../openFPGALoader/spiOverJtag/xilinx_spiOverJtag.v:92]

For the Spartan 6 FPGA, a bitstream is created, but the final tar.gz file is not generated.
Similarly, no tar.gz file is created for xc7k325tffg676 and xc7k420tffg901. Although for xc7k70tfbg484 and xc7k160tffg676, the archive is created because Vivado tool is used for the build, and the archive creation process has been transferred from the Makefile to the script build.py

[trabucayre]

Thanks to point me this issue: a regression during v1 -> v2
Will check this

[trabucayre]

spartan3e built is fixed by 06b4e2f

[pkuzmin]

spartan3e built is fixed by 06b4e2f

spartan3e still requires such changes

diff --git a/spiOverJtag/xilinx_spiOverJtag.v b/spiOverJtag/xilinx_spiOverJtag.v
index e18da9a..1b14f03 100644
--- a/spiOverJtag/xilinx_spiOverJtag.v
+++ b/spiOverJtag/xilinx_spiOverJtag.v
@@ -27,11 +27,11 @@ module spiOverJtag

        wire capture, drck, sel, update, shift;
        wire tdi, tdo;
-       wire spi_clk;

 `ifndef spartan3e
        /* Version Interface. */
        wire ver_sel, ver_cap, ver_shift, ver_drck, ver_tdi, ver_tdo;
+       wire spi_clk;

        spiOverJtag_core spiOverJtag_core_prim (
                /* JTAG state/controls */
@@ -65,7 +65,7 @@ module spiOverJtag
        assign sck = spi_clk;
 `else // !spartan6
 `ifdef spartan3e
-       assign sck = spi_clk;
+       assign sck = drck;
 `else // !spartan6 && !spartan3e
 `ifdef xilinxultrascale
        assign sck = drck;

and more changes in order to allow operations with flash

diff --git a/src/xilinx.cpp b/src/xilinx.cpp
index 5156654..ed1de25 100644
--- a/src/xilinx.cpp
+++ b/src/xilinx.cpp
@@ -365,9 +365,6 @@ Xilinx::Xilinx(Jtag *jtag, const std::string &filename,
                _ircode_map = ircode_mapping.at("virtexusp");
        } else if (family.substr(0, 8) == "spartan3") {
                _fpga_family = SPARTAN3_FAMILY;
-               if (_mode != Device::MEM_MODE) {
-                       throw std::runtime_error("Error: Only load to mem is supported");
-               }
        } else if (family == "xcf") {
                _fpga_family = XCF_FAMILY;
                if (_mode == Device::MEM_MODE) {

[trabucayre]

Indeed. It's now fixed but can't test by myself: my only spartan3 board has a Flash accessible via JTAG

[trabucayre]

With 29a5bc3 virtex build success
I have also fixed tar.gz generation.
Thanks!

[pkuzmin]

Indeed. It's now fixed but can't test by myself: my only spartan3 board has a Flash accessible via JTAG

Thank you for your work.
There is one error in the 1ccc2a0 commit.

Compiling verilog file "../xilinx_spiOverJtag.v" in library work
ERROR:HDLCompilers:28 - "../xilinx_spiOverJtag.v" line 74 'spi_drck' has not been declared

I think it should be like this

diff --git a/spiOverJtag/xilinx_spiOverJtag.v b/spiOverJtag/xilinx_spiOverJtag.v
index 3fa93ef..4406029 100644
--- a/spiOverJtag/xilinx_spiOverJtag.v
+++ b/spiOverJtag/xilinx_spiOverJtag.v
@@ -71,7 +71,7 @@ module spiOverJtag
        assign sck = spi_clk;
 `else // !spartan6
 `ifdef spartan3e
-       assign sck = spi_drck;
+       assign sck = drck;
 `else // !spartan6 && !spartan3e
 `ifdef xilinxultrascale
        assign sck = drck;

[trabucayre]

Indeed: thanks.
Fixed with fdc9edc
But look like xilinx_spiOverJtag.v is a bit too complex with too many ifdef.

[pkuzmin]

Commit 8e6eb10 broke the ISE build

$ make spiOverJtag_xc3s500evq100.bit.gz
./build.py xc3s500evq100
Successfully created the directory tmp_xc3s500evq100
Traceback (most recent call last):
  File "/home/pk/test/openFPGALoader/spiOverJtag/./build.py", line 184, in <module>
    }.get(part, pkg),
                ^^^
NameError: name 'pkg' is not defined
make: *** [Makefile:39: tmp_xc3s500evq100/spiOverJtag.bit] Error 1

$ make spiOverJtag_xc7k325tffg676.bit.gz
./build.py xc7k325tffg676
Successfully created the directory tmp_xc7k325tffg676
make[1]: Entering directory '/home/pk/test/openFPGALoader/spiOverJtag/tmp_xc7k325tffg676'
xtclsh spiOverJtag.tcl
ERROR:TclTasksC:project_029: Ambiguous property value "xc7k"
Matches:

 "xc7k70t"
 "xc7k160t"
 "xc7k325t"
 "xc7k355t"
 "xc7k410t"
 "xc7k420t"
 "xc7k480t"

Please choose one of the possible matches and re-try the command. Specify the exact value if duplicate matches were found.
    while executing
"project set device xc7k"
    (file "spiOverJtag.tcl" line 16)
make[1]: *** [Makefile:10: spiOverJtag.xise] Error 1

Why is ISE used for kintex7 with more than 160t capacity?

[trabucayre]

First issue is fixed by f8ae76e
Second issue fixed by 205e6f9

But seems clear this code must be simplied a lot.

For ISE used for kintex > 160, it's something added by @hansfbaier because actual ISE's license are not limited to size, unlike vivado requiring full license for this range of the Kintex family (4c0f683 and #224).