Error when loading Virtex5

[mert-ekren]

Greetings I was using Virtex5 to load MCS file for bootloader of a virtex5 series fpga and i get this error JTAG init failed with: Unknown device with IDCODE: 0x32ece093 (manufacturer (Xilinx), part: 0x17 vers: 0x3, i know that it doesnt support virtex 5 is there an extension posibility, i am mainly using the trimode ethernet for ee5410.

[trabucayre]

openFPGALoader needs to now some basics informations about the device. This is done via part.hpp where for all models the IDCODE (here: 0x32ece093) is associated with a manufacturer, a family, a model and an IR length.
Since no virtex5 are present in openFPGALoader, the IDCODE is unknown and consequently openFPGALoader has no informations.

To adds support you have first to update part.hpp to add a new entry for your device and test as it. It also maybe possible some adjustements are required since xilinx.cpp has no informations about virtex5.
First of all is to add IDCODE in part.hpp and test if basic functionnalities are working (loading into SRAM).

[mert-ekren]

i have managed to load the sram without an issue but since the virtex5 is not supported originally it cannot be loaded with -f command is it possible to add virtex5 xc5vsx95t to the supported boards in the SpiOverJtag

[trabucayre]

I will try to generates the correct spiOverJtag bitstream but I need the full reference (including package)

[mert-ekren]

Family = Virtex5
Device = xc5vsx95t
Package = ff1136
Speed = -2

[trabucayre]

Have you board schematic? The Virtex5 may be used with differents type of flash, and since I haven't this device it's more easy to have much informations.
I suspect this model is more or less equivalent to virtex6

[mert-ekren]

I believe these should suffice

[trabucayre]

Could you try with this bitstream:
spiOverJtag_xc5vsx95tff1136.bit.gz

[mert-ekren]

Sorry fir the delayed response, it has a small issue when i send the command openFPGALoader -c digilent_hsn3 --index-chain 0 --fpga-part xc5vx95t -f smthing.bin --unprotect-flash it gives the following

[trabucayre]

Okay I see 2 issues here:

• after the bitstream is loaded the FPGAs seems not ready: datasheet must be checked to see if something specific/delay must be added (loop or something like this?)
• you have more than one FPGA in your JTAG chain, but the spiOverJtag v2 has not being tested on this device and the bitstream is build with v1 model (not supporting more than one FPGA).

I will try to find/improves support for this model, but it usually more easy to have a physical access to the FPGA. I can't bought a board with this device because, it's too expensive.

I think to be able to access the virtex5 you have applied some modifications? Is it possible for you to share?