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[RISCV] Add Zic64b, Ziccamoa, Ziccif, Zicclsm, Ziccrse, and Za64rs to sifive-p450. (llvm#79030)
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clang/test/Driver/riscv-cpus.c

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@@ -228,14 +228,20 @@
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// MCPU-SIFIVE-P450-SAME: "-target-feature" "+f"
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// MCPU-SIFIVE-P450-SAME: "-target-feature" "+d"
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// MCPU-SIFIVE-P450-SAME: "-target-feature" "+c"
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// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zic64b"
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// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zicbom"
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// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zicbop"
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// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zicboz"
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// MCPU-SIFIVE-P450-SAME: "-target-feature" "+ziccamoa"
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// MCPU-SIFIVE-P450-SAME: "-target-feature" "+ziccif"
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// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zicclsm"
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// MCPU-SIFIVE-P450-SAME: "-target-feature" "+ziccrse"
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// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zicsr"
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// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zifencei"
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// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zihintntl"
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// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zihintpause"
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// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zihpm"
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// MCPU-SIFIVE-P450-SAME: "-target-feature" "+za64rs"
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// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zfhmin"
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// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zba"
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// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbb"

llvm/lib/Target/RISCV/RISCVProcessors.td

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@@ -223,9 +223,15 @@ def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", SiFiveP400Model,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC,
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FeatureStdExtZa64rs,
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FeatureStdExtZic64b,
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FeatureStdExtZicbop,
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FeatureStdExtZicbom,
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FeatureStdExtZicboz,
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FeatureStdExtZiccamoa,
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FeatureStdExtZiccif,
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FeatureStdExtZicclsm,
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FeatureStdExtZiccrse,
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FeatureStdExtZihintntl,
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FeatureStdExtZihintpause,
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FeatureStdExtZihpm,

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