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ekilmerekilmer
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Upgrade mypy and linting fixes
1 parent 38a261c commit 6d3d72c

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12 files changed

+84
-107
lines changed

12 files changed

+84
-107
lines changed

‎manticore/core/smtlib/expression.py‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1168,7 +1168,7 @@ def __init__(self, array: Array, index: BitVec, value: BitVec, **kwargs):
11681168
assert index.size == array.index_size
11691169
assert value.size == array.value_size
11701170
self._written: Optional[Set[Any]] = None # Cache of the known indexes
1171-
self._concrete_cache: Dict[Any, Any] = None
1171+
self._concrete_cache: Optional[Dict[Any, Any]] = None
11721172
self._length = array.length
11731173
self._default = array.default
11741174

‎manticore/core/state.py‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
import copy
22
import logging
3-
from typing import Any, Dict, List, Optional, TYPE_CHECKING
3+
from typing import Any, Dict, List, Optional, TypeVar, TYPE_CHECKING
44

55
from .smtlib import Bool, ConstraintSet, Expression, issymbolic, BitVecConstant, MutableArray
66
from ..utils.event import Eventful
@@ -172,8 +172,8 @@ class StateBase(Eventful):
172172
"""
173173
Representation of a unique program state/path.
174174
175-
:param ConstraintSet constraints: Initial constraints
176-
:param Platform platform: Initial operating system state
175+
:param constraints: Initial constraints
176+
:param platform: Initial operating system state
177177
:ivar dict context: Local context for arbitrary data storage
178178
"""
179179

@@ -183,7 +183,7 @@ def __init__(
183183
self,
184184
*,
185185
constraints: ConstraintSet,
186-
platform: "Platform",
186+
platform: Platform,
187187
manticore: Optional["ManticoreBase"] = None,
188188
**kwargs,
189189
):

‎manticore/native/cpu/aarch64.py‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,7 @@ class Aarch64InvalidInstruction(CpuException):
4040

4141

4242
# See "C1.2.4 Condition code".
43-
Condspec = collections.namedtuple("CondSpec", "inverse func")
43+
Condspec = collections.namedtuple("Condspec", "inverse func")
4444
COND_MAP = {
4545
cs.arm64.ARM64_CC_EQ: Condspec(cs.arm64.ARM64_CC_NE, lambda n, z, c, v: z == 1),
4646
cs.arm64.ARM64_CC_NE: Condspec(cs.arm64.ARM64_CC_EQ, lambda n, z, c, v: z == 0),
@@ -75,7 +75,7 @@ class Aarch64InvalidInstruction(CpuException):
7575

7676

7777
class Aarch64RegisterFile(RegisterFile):
78-
Regspec = collections.namedtuple("RegSpec", "parent size")
78+
Regspec = collections.namedtuple("Regspec", "parent size")
7979

8080
# Register table.
8181
_table = {}

‎manticore/native/cpu/x86.py‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -144,7 +144,7 @@ def new_method(cpu, *args, **kw_args):
144144

145145

146146
class AMD64RegFile(RegisterFile):
147-
Regspec = collections.namedtuple("RegSpec", "register_id ty offset size reset")
147+
Regspec = collections.namedtuple("Regspec", "register_id ty offset size reset")
148148
_flags = {"CF": 0, "PF": 2, "AF": 4, "ZF": 6, "SF": 7, "IF": 9, "DF": 10, "OF": 11}
149149
_table = {
150150
"CS": Regspec("CS", int, 0, 16, False),

‎manticore/native/state.py‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -11,9 +11,10 @@
1111
from ..platforms import linux_syscalls
1212

1313
if TYPE_CHECKING:
14-
from ..platforms.platform import Platform
14+
from ..platforms.linux import Linux
15+
from ..platforms.decree import Decree
1516

16-
HookCallback = Callable[[StateBase], None]
17+
HookCallback = Callable[["State"], None]
1718
logger = logging.getLogger(__name__)
1819

1920

@@ -23,7 +24,7 @@ class CheckpointData(NamedTuple):
2324

2425

2526
class State(StateBase):
26-
def __init__(self, *, constraints: ConstraintSet, platform: "Platform", **kwargs):
27+
def __init__(self, *, constraints: ConstraintSet, platform: Union[Linux, Decree], **kwargs):
2728
super().__init__(constraints=constraints, platform=platform, **kwargs)
2829
self._hooks: Dict[Optional[int], Set[HookCallback]] = {}
2930
self._after_hooks: Dict[Optional[int], Set[HookCallback]] = {}

‎manticore/platforms/platform.py‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,10 @@
11
import logging
2-
from typing import Optional
3-
42
from functools import wraps
5-
from typing import Any, Callable, TypeVar
3+
from typing import Any, Callable, TypeVar, Optional
64

75
from ..utils.event import Eventful
86
from ..core.state import StateBase
7+
from ..native.cpu.abstractcpu import Cpu
98

109

1110
logger = logging.getLogger(__name__)
@@ -50,6 +49,8 @@ class Platform(Eventful):
5049
Base class for all platforms e.g. operating systems or virtual machines.
5150
"""
5251

52+
current: Any
53+
5354
_published_events = {"solve"}
5455

5556
def __init__(self, *, state: Optional[StateBase] = None, **kwargs):

‎mypy.ini‎

Lines changed: 1 addition & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
[mypy]
22
python_version = 3.6
33
files = manticore, tests, examples/**/*.py
4+
ignore_missing_imports = True
45
# TODO: LOTS OF ERRORS
56
# check_untyped_defs = True
67

@@ -11,45 +12,5 @@ check_untyped_defs = True
1112
[mypy-manticore.ethereum.parsetab]
1213
ignore_errors = True
1314

14-
# 3rd-party libraries with no typing information
15-
[mypy-capstone.*]
16-
ignore_missing_imports = True
17-
18-
[mypy-crytic_compile.*]
19-
ignore_missing_imports = True
20-
21-
[mypy-elftools.*]
22-
ignore_missing_imports = True
23-
24-
[mypy-sha3.*]
25-
ignore_missing_imports = True
26-
27-
[mypy-pyevmasm.*]
28-
ignore_missing_imports = True
29-
30-
[mypy-unicorn.*]
31-
ignore_missing_imports = True
32-
33-
[mypy-keystone.*]
34-
ignore_missing_imports = True
35-
36-
[mypy-ply.*]
37-
ignore_missing_imports = True
38-
39-
[mypy-rlp.*]
40-
ignore_missing_imports = True
41-
42-
[mypy-setuptools.*]
43-
ignore_missing_imports = True
44-
45-
[mypy-toposort.*]
46-
ignore_missing_imports = True
47-
48-
[mypy-prettytable.*]
49-
ignore_missing_imports = True
50-
51-
[mypy-wasm.*]
52-
ignore_missing_imports = True
53-
5415
[mypy-manticore.core.state_pb2]
5516
ignore_errors = True

‎setup.py‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ def rtd_dependent_deps():
1818
# (we need to know how to import a given native dependency so we can check if native dependencies are installed)
1919
native_deps = ["capstone==4.0.1", "pyelftools", "unicorn==1.0.2rc2"]
2020

21-
lint_deps = ["black==20.8b1", "mypy==0.790"]
21+
lint_deps = ["black==20.8b1", "mypy==0.812"]
2222

2323
auto_test_deps = ["py-evm"]
2424

‎tests/auto_generators/flags.py‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,6 @@
1-
flags = {
1+
from typing import Dict, List
2+
3+
flags: Dict[str, Dict[str, List[str]]] = {
24
"AAA": {
35
"undefined": ["OF", "SF", "ZF", "PF"],
46
"defined": ["AF", "CF"],

‎tests/auto_generators/make_dump.py‎

Lines changed: 39 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,10 @@
55
import sys
66
import time
77
import subprocess
8-
from capstone import *
9-
from capstone.x86 import *
8+
from typing import Any, Dict
9+
from capstone import Cs
10+
from capstone.x86 import CS_ARCH_X86, CS_MODE_32, CS_MODE_64, X86_OP_MEM, X86_OP_REG, X86_OP_IMM
11+
import capstone.x86 as csr
1012
from flags import flags
1113

1214
flags_maks = {
@@ -228,7 +230,7 @@ def read_operand(o):
228230
groups = map(instruction.group_name, instruction.groups)
229231

230232
PC = {"i386": "EIP", "amd64": "RIP"}[arch]
231-
registers = {PC: gdb.getR(PC)}
233+
registers: Dict[Any, Any] = {PC: gdb.getR(PC)}
232234
memory = {}
233235

234236
# save the encoded instruction
@@ -246,11 +248,11 @@ def read_operand(o):
246248
if instruction.insn_name().upper() in ["PUSHF", "PUSHFD"]:
247249
registers["EFLAGS"] = gdb.getR("EFLAGS")
248250

249-
if instruction.insn_name().upper() in ["XLAT", "XLATB"]:
250-
registers["AL"] = gdb.getR("AL")
251-
registers[B] = gdb.getR(B)
252-
address = registers[B] + registers["AL"]
253-
memory[address] = chr(gdb.getByte(address))
251+
# if instruction.insn_name().upper() in ["XLAT", "XLATB"]:
252+
# registers["AL"] = gdb.getR("AL")
253+
# registers[B] = gdb.getR(B)
254+
# address = registers[B] + registers["AL"]
255+
# memory[address] = chr(gdb.getByte(address))
254256

255257
if instruction.insn_name().upper() in ["BTC", "BTR", "BTS", "BT"]:
256258
if instruction.operands[0].type == X86_OP_MEM:
@@ -310,34 +312,34 @@ def read_operand(o):
310312
# registers[reg_name] = gdb.getR(reg_name)
311313

312314
reg_sizes = {
313-
X86_REG_AH: X86_REG_AX,
314-
X86_REG_AL: X86_REG_AX,
315-
X86_REG_AX: X86_REG_EAX,
316-
X86_REG_EAX: X86_REG_RAX,
317-
X86_REG_RAX: X86_REG_INVALID,
318-
X86_REG_BH: X86_REG_BX,
319-
X86_REG_BL: X86_REG_BX,
320-
X86_REG_BX: X86_REG_EBX,
321-
X86_REG_EBX: X86_REG_RBX,
322-
X86_REG_RBX: X86_REG_INVALID,
323-
X86_REG_CH: X86_REG_CX,
324-
X86_REG_CL: X86_REG_CX,
325-
X86_REG_CX: X86_REG_ECX,
326-
X86_REG_ECX: X86_REG_RCX,
327-
X86_REG_RCX: X86_REG_INVALID,
328-
X86_REG_DH: X86_REG_DX,
329-
X86_REG_DL: X86_REG_DX,
330-
X86_REG_DX: X86_REG_EDX,
331-
X86_REG_EDX: X86_REG_RDX,
332-
X86_REG_RDX: X86_REG_INVALID,
333-
X86_REG_DIL: X86_REG_EDI,
334-
X86_REG_DI: X86_REG_EDI,
335-
X86_REG_EDI: X86_REG_RDI,
336-
X86_REG_RDI: X86_REG_INVALID,
337-
X86_REG_SIL: X86_REG_ESI,
338-
X86_REG_SI: X86_REG_ESI,
339-
X86_REG_ESI: X86_REG_RSI,
340-
X86_REG_RSI: X86_REG_INVALID,
315+
csr.X86_REG_AH: csr.X86_REG_AX,
316+
csr.X86_REG_AL: csr.X86_REG_AX,
317+
csr.X86_REG_AX: csr.X86_REG_EAX,
318+
csr.X86_REG_EAX: csr.X86_REG_RAX,
319+
csr.X86_REG_RAX: csr.X86_REG_INVALID,
320+
csr.X86_REG_BH: csr.X86_REG_BX,
321+
csr.X86_REG_BL: csr.X86_REG_BX,
322+
csr.X86_REG_BX: csr.X86_REG_EBX,
323+
csr.X86_REG_EBX: csr.X86_REG_RBX,
324+
csr.X86_REG_RBX: csr.X86_REG_INVALID,
325+
csr.X86_REG_CH: csr.X86_REG_CX,
326+
csr.X86_REG_CL: csr.X86_REG_CX,
327+
csr.X86_REG_CX: csr.X86_REG_ECX,
328+
csr.X86_REG_ECX: csr.X86_REG_RCX,
329+
csr.X86_REG_RCX: csr.X86_REG_INVALID,
330+
csr.X86_REG_DH: csr.X86_REG_DX,
331+
csr.X86_REG_DL: csr.X86_REG_DX,
332+
csr.X86_REG_DX: csr.X86_REG_EDX,
333+
csr.X86_REG_EDX: csr.X86_REG_RDX,
334+
csr.X86_REG_RDX: csr.X86_REG_INVALID,
335+
csr.X86_REG_DIL: csr.X86_REG_EDI,
336+
csr.X86_REG_DI: csr.X86_REG_EDI,
337+
csr.X86_REG_EDI: csr.X86_REG_RDI,
338+
csr.X86_REG_RDI: csr.X86_REG_INVALID,
339+
csr.X86_REG_SIL: csr.X86_REG_ESI,
340+
csr.X86_REG_SI: csr.X86_REG_ESI,
341+
csr.X86_REG_ESI: csr.X86_REG_RSI,
342+
csr.X86_REG_RSI: csr.X86_REG_INVALID,
341343
}
342344
# There is a capstone branch that should fix all these annoyances... soon
343345
# https://github.com/aquynh/capstone/tree/next
@@ -387,7 +389,7 @@ def read_operand(o):
387389
registers[reg_name] = gdb.getR(reg_name)
388390
address += o.mem.scale * registers[reg_name]
389391
address = address & ({"i386": 0xFFFFFFFF, "amd64": 0xFFFFFFFFFFFFFFFF}[arch])
390-
for i in xrange(address, address + o.size):
392+
for i in range(address, address + o.size):
391393
memory[i] = chr(gdb.getByte(i))
392394

393395
# gather PRE info

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