[BACKEND] bump to llvm/llvm-project@71a977d0d611 (#6334)

Waiting on
https://github.com/triton-lang/triton/actions/runs/14136666457

Author: makslevental

cmake/llvm-hash.txt

@@ -1 +1 @@
-0ea4fb92648b2aa7cbab486bb493e122b4dcc062
+71a977d0d611f3e9f6137a6b8a26b730b2886ce9

python/test/unit/language/test_compile_only.py

@@ -54,7 +54,7 @@ def simple_dot(a_base, b_base, out):
     assert re.search(pattern, str(ttgir)), "The TTGIR does not match the expected pattern."
 
     ptx = k.asm["ptx"]
-    pattern = (r"mov\.u32 	%r(?P<G>\d+), global_smem;"
+    pattern = (r"mov\.b32 	%r(?P<G>\d+), global_smem;"
                r"(.|\n)*"
                r"tcgen05\.alloc\.cta_group::1\.sync\.aligned\.shared::cta\.b32 \[%r(?P=G)], 64"
                r"(.|\n)*"

third_party/amd/lib/TritonAMDGPUToLLVM/LoadStoreOpToLLVM.cpp

@@ -588,12 +588,15 @@ struct AsyncCopyGlobalToLocalOpConversion
     // size
     for (int i = 0; i < shmemAddrs.size(); i++) {
       auto srcIdx = i * maxVec;
-      auto srcPtr = srcElems[srcIdx];
+      Value srcPtr = srcElems[srcIdx];
 
       if (maskElems.empty()) {
         rewriter.create<ROCDL::GlobalLoadLDSOp>(
-            loc, srcPtr, shmemAddrs[i], vecBytesVal, /*offset=*/b.i32_val(0),
-            cacheModifiers);
+            loc,
+            /*globalPtr=*/srcPtr, /*ldsPtr=*/shmemAddrs[i],
+            /*size=*/vecBytesVal, /*offset=*/b.i32_val(0),
+            /*aux=*/cacheModifiers, /*alias_scopes=*/nullptr,
+            /*noalias_scopes=*/nullptr, /*tbaa=*/nullptr);
         continue;
       }
 
@@ -607,7 +610,7 @@ struct AsyncCopyGlobalToLocalOpConversion
       rewriter.setInsertionPointToStart(loadBlock);
       rewriter.create<ROCDL::GlobalLoadLDSOp>(
           loc, srcPtr, shmemAddrs[i], vecBytesVal, /*offset=*/b.i32_val(0),
-          cacheModifiers);
+          cacheModifiers, nullptr, nullptr, nullptr);
 
       rewriter.create<LLVM::BrOp>(loc, afterLoad);
       rewriter.setInsertionPointToStart(afterLoad);