@@ -220,6 +220,30 @@ static const char *TAG = "WLED";
220220 host_config.intr_flags = ESP_INTR_FLAG_LEVEL1;
221221 host_config.peripheral_map = BIT (0 );
222222
223+ // Bias Mode nptx_fifo_lines ptx_fifo_lines rx_fifo_lines
224+ // Balanced 256 128 512 (896 - 256 - 128)
225+ // IN-Biased 64 128 704 (896 - 64 - 128) <--- does not work, but 896 seenms to be the correct total, confirmed by reading out the register.
226+
227+ // Balanced values work: (works! and seem to match the IDF built with balanced defaults)
228+ // host_config.fifo_settings_custom.nptx_fifo_lines = 256;
229+ // host_config.fifo_settings_custom.ptx_fifo_lines = 128;
230+ // host_config.fifo_settings_custom.rx_fifo_lines = 512;
231+
232+ // Testing a mid point: (marginal winner!)
233+ // (tried a bunch off other ones too, this was the best - they were worse than balanced)
234+ //
235+ host_config.fifo_settings_custom .nptx_fifo_lines = 128 ;
236+ host_config.fifo_settings_custom .ptx_fifo_lines = 128 ;
237+ host_config.fifo_settings_custom .rx_fifo_lines = 640 ;
238+
239+ // If you need to know your on-SOC FIFO numbers this is the code - just for checking the register on the P4.
240+ // (The answer is 896, at least on all the current P4 devices I have.)
241+ //
242+ // periph_module_enable(PERIPH_UHCI_MODULE);
243+ // uint16_t fifo_depth_value = USB_DWC_HS.ghwcfg3_reg.dfifodepth;
244+ // USER_PRINTF("*** Extracted dfifodepth (fifo_size_lines): %u\n", fifo_depth_value);
245+ // periph_module_disable(PERIPH_UHCI_MODULE);
246+
223247 ESP_ERROR_CHECK (usb_host_install (&host_config));
224248
225249 const msc_host_driver_config_t msc_config = {
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