clk: sunxi-ng: v3s: Fix TCON clock parents

The TCON clock can be parented to both the video PLL and the periph0 PLL.
Add the latter, which was missing from the list.

Fixes: d0f11d1 ("clk: sunxi-ng: add support for V3s CCU")
Signed-off-by: Paul Kocialkowski <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Chen-Yu Tsai <[email protected]>

Author: paulkocialkowski

drivers/clk/sunxi-ng/ccu-sun8i-v3s.c

@@ -350,7 +350,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
 				 0x104, 0, 4, 24, 2, BIT(31),
 				 CLK_SET_RATE_PARENT);
 
-static const char * const tcon_parents[] = { "pll-video" };
+static const char * const tcon_parents[] = { "pll-video", "pll-periph0" };
 static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,
 				 0x118, 0, 4, 24, 3, BIT(31), 0);