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Merge tag 'drm-fixes-2025-08-29' of https://gitlab.freedesktop.org/drm/kernel
Pull drm fixes from Dave Airlie: "Weekly fixes, feels a bit big. The major piece is msm fixes, then the usual amdgpu/xe along with some mediatek and nouveau fixes and a tegra revert. gpuvm: - fix some typos xe: - Fix user-fence race issue - Couple xe_vm fixes - Don't trigger rebind on initial dma-buf validation - Fix a build issue related to basename() posix vs gnu discrepancy amdgpu: - pin buffers while vmapping - UserQ fixes - Revert CSA fix - SR-IOV fix nouveau: - fix linear modifier - remove some dead code msm: - Core/GPU: - fix comment doc warning in gpuvm - fix build with KMS disabled - fix pgtable setup/teardown race - global fault counter fix - various error path fixes - GPU devcoredump snapshot fixes - handle in-place VM_BIND remaps to solve turnip vm update race - skip re-emitting IBs for unusable VMs - Don't use %pK through printk - moved display snapshot init earlier, fixing a crash - DPU: - Fixed crash in virtual plane checking code - Fixed mode comparison in virtual plane checking code - DSI: - Adjusted width of resulution-related registers - Fixed locking issue on 14nm PLLs - UBWC (per Bjorn's ack) - Added UBWC configuration for several missing platforms (fixing regression) mediatek: - Add error handling for old state CRTC in atomic_disable - Fix DSI host and panel bridge pre-enable order - Fix device/node reference count leaks in mtk_drm_get_all_drm_priv - mtk_hdmi: Fix inverted parameters in some regmap_update_bits calls tegra: - revert dma-buf change" * tag 'drm-fixes-2025-08-29' of https://gitlab.freedesktop.org/drm/kernel: (56 commits) drm/mediatek: mtk_hdmi: Fix inverted parameters in some regmap_update_bits calls drm/amdgpu/userq: fix error handling of invalid doorbell drm/amdgpu: update firmware version checks for user queue support drm/amd/amdgpu: disable hwmon power1_cap* for gfx 11.0.3 on vf mode Revert "drm/amdgpu: fix incorrect vm flags to map bo" drm/amdgpu/gfx12: set MQD as appriopriate for queue types drm/amdgpu/gfx11: set MQD as appriopriate for queue types drm/xe: switch to local xbasename() helper drm/xe: Don't trigger rebind on initial dma-buf validation drm/xe/vm: Clear the scratch_pt pointer on error drm/xe/vm: Don't pin the vm_resv during validation drm/xe/xe_sync: avoid race during ufence signaling Revert "drm/tegra: Use dma_buf from GEM object instance" soc: qcom: use no-UBWC config for MSM8956/76 soc: qcom: add configuration for MSM8929 soc: qcom: ubwc: add more missing platforms soc: qcom: ubwc: use no-uwbc config for MSM8917 drm/msm/dpu: Add a null ptr check for dpu_encoder_needs_modeset dt-bindings: display/msm: qcom,mdp5: drop lut clock drm/gpuvm: fix various typos in .c and .h gpuvm file ...
2 parents d1cf752 + 42d2abb commit 18ee2b9

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lines changed

‎Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -60,7 +60,6 @@ properties:
6060
- const: bus
6161
- const: core
6262
- const: vsync
63-
- const: lut
6463
- const: tbu
6564
- const: tbu_rt
6665
# MSM8996 has additional iommu clock

‎drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -88,8 +88,8 @@ int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm,
8888
}
8989

9090
r = amdgpu_vm_bo_map(adev, *bo_va, csa_addr, 0, size,
91-
AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
92-
AMDGPU_VM_PAGE_EXECUTABLE);
91+
AMDGPU_PTE_READABLE | AMDGPU_PTE_WRITEABLE |
92+
AMDGPU_PTE_EXECUTABLE);
9393

9494
if (r) {
9595
DRM_ERROR("failed to do bo_map on static CSA, err=%d\n", r);

‎drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c‎

Lines changed: 32 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -285,6 +285,36 @@ static int amdgpu_dma_buf_begin_cpu_access(struct dma_buf *dma_buf,
285285
return ret;
286286
}
287287

288+
static int amdgpu_dma_buf_vmap(struct dma_buf *dma_buf, struct iosys_map *map)
289+
{
290+
struct drm_gem_object *obj = dma_buf->priv;
291+
struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
292+
int ret;
293+
294+
/*
295+
* Pin to keep buffer in place while it's vmap'ed. The actual
296+
* domain is not that important as long as it's mapable. Using
297+
* GTT and VRAM should be compatible with most use cases.
298+
*/
299+
ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM);
300+
if (ret)
301+
return ret;
302+
ret = drm_gem_dmabuf_vmap(dma_buf, map);
303+
if (ret)
304+
amdgpu_bo_unpin(bo);
305+
306+
return ret;
307+
}
308+
309+
static void amdgpu_dma_buf_vunmap(struct dma_buf *dma_buf, struct iosys_map *map)
310+
{
311+
struct drm_gem_object *obj = dma_buf->priv;
312+
struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
313+
314+
drm_gem_dmabuf_vunmap(dma_buf, map);
315+
amdgpu_bo_unpin(bo);
316+
}
317+
288318
const struct dma_buf_ops amdgpu_dmabuf_ops = {
289319
.attach = amdgpu_dma_buf_attach,
290320
.pin = amdgpu_dma_buf_pin,
@@ -294,8 +324,8 @@ const struct dma_buf_ops amdgpu_dmabuf_ops = {
294324
.release = drm_gem_dmabuf_release,
295325
.begin_cpu_access = amdgpu_dma_buf_begin_cpu_access,
296326
.mmap = drm_gem_dmabuf_mmap,
297-
.vmap = drm_gem_dmabuf_vmap,
298-
.vunmap = drm_gem_dmabuf_vunmap,
327+
.vmap = amdgpu_dma_buf_vmap,
328+
.vunmap = amdgpu_dma_buf_vunmap,
299329
};
300330

301331
/**

‎drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -471,6 +471,7 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args)
471471
if (index == (uint64_t)-EINVAL) {
472472
drm_file_err(uq_mgr->file, "Failed to get doorbell for queue\n");
473473
kfree(queue);
474+
r = -EINVAL;
474475
goto unlock;
475476
}
476477

‎drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c‎

Lines changed: 9 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1612,9 +1612,9 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
16121612
case IP_VERSION(11, 0, 2):
16131613
case IP_VERSION(11, 0, 3):
16141614
if (!adev->gfx.disable_uq &&
1615-
adev->gfx.me_fw_version >= 2390 &&
1616-
adev->gfx.pfp_fw_version >= 2530 &&
1617-
adev->gfx.mec_fw_version >= 2600 &&
1615+
adev->gfx.me_fw_version >= 2420 &&
1616+
adev->gfx.pfp_fw_version >= 2580 &&
1617+
adev->gfx.mec_fw_version >= 2650 &&
16181618
adev->mes.fw_version[0] >= 120) {
16191619
adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs;
16201620
adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs;
@@ -4129,6 +4129,8 @@ static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
41294129
#endif
41304130
if (prop->tmz_queue)
41314131
tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, TMZ_MATCH, 1);
4132+
if (!prop->kernel_queue)
4133+
tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_NON_PRIV, 1);
41324134
mqd->cp_gfx_hqd_cntl = tmp;
41334135

41344136
/* set up cp_doorbell_control */
@@ -4281,8 +4283,10 @@ static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
42814283
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
42824284
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH,
42834285
prop->allow_tunneling);
4284-
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
4285-
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
4286+
if (prop->kernel_queue) {
4287+
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
4288+
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
4289+
}
42864290
if (prop->tmz_queue)
42874291
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TMZ, 1);
42884292
mqd->cp_hqd_pq_control = tmp;

‎drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3026,6 +3026,8 @@ static int gfx_v12_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
30263026
#endif
30273027
if (prop->tmz_queue)
30283028
tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, TMZ_MATCH, 1);
3029+
if (!prop->kernel_queue)
3030+
tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_NON_PRIV, 1);
30293031
mqd->cp_gfx_hqd_cntl = tmp;
30303032

30313033
/* set up cp_doorbell_control */
@@ -3175,8 +3177,10 @@ static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
31753177
(order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
31763178
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
31773179
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
3178-
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3179-
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3180+
if (prop->kernel_queue) {
3181+
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3182+
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3183+
}
31803184
if (prop->tmz_queue)
31813185
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TMZ, 1);
31823186
mqd->cp_hqd_pq_control = tmp;

‎drivers/gpu/drm/amd/pm/amdgpu_pm.c‎

Lines changed: 10 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -3458,14 +3458,16 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
34583458
effective_mode &= ~S_IWUSR;
34593459

34603460
/* not implemented yet for APUs other than GC 10.3.1 (vangogh) and 9.4.3 */
3461-
if (((adev->family == AMDGPU_FAMILY_SI) ||
3462-
((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(10, 3, 1)) &&
3463-
(gc_ver != IP_VERSION(9, 4, 3) && gc_ver != IP_VERSION(9, 4, 4)))) &&
3464-
(attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
3465-
attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr ||
3466-
attr == &sensor_dev_attr_power1_cap.dev_attr.attr ||
3467-
attr == &sensor_dev_attr_power1_cap_default.dev_attr.attr))
3468-
return 0;
3461+
if (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
3462+
attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr ||
3463+
attr == &sensor_dev_attr_power1_cap.dev_attr.attr ||
3464+
attr == &sensor_dev_attr_power1_cap_default.dev_attr.attr) {
3465+
if (adev->family == AMDGPU_FAMILY_SI ||
3466+
((adev->flags & AMD_IS_APU) && gc_ver != IP_VERSION(10, 3, 1) &&
3467+
(gc_ver != IP_VERSION(9, 4, 3) && gc_ver != IP_VERSION(9, 4, 4))) ||
3468+
(amdgpu_sriov_vf(adev) && gc_ver == IP_VERSION(11, 0, 3)))
3469+
return 0;
3470+
}
34693471

34703472
/* not implemented yet for APUs having < GC 9.3.0 (Renoir) */
34713473
if (((adev->family == AMDGPU_FAMILY_SI) ||

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