forwarding_unit: fix stale cache-hit load data in int->fp forwarding

  Use MA-stage load data as the single source of truth for dependent load forwarding
  into int->fp conversions and MA bypass paths.

  Root cause:

  - On cache-hit load dependencies, forwarding selected
    i_from_cache.data_loaded_from_cache_reg.
  - That registered cache value can be stale relative to the current MA load result,
    causing incorrect operands for dependent fcvt.d.w operations.

  Fix:

  - Set int_capture_bypass_data to i_from_ma_comb.data_loaded_from_memory.
  - For forward_data_ma cache-hit forwarding, use
    i_from_ma_comb.data_loaded_from_memory instead of
    i_from_cache.data_loaded_from_cache_reg.
  - Keep cache-hit dependency detection logic, but source forwarded data from MA.

  Validation:

  - test_run_cocotb.py --sim verilator cpu --random-seed=1772418093
  - CPU cocotb regression summary: TESTS=21 PASS=21 FAIL=0

Author: adambagley

hw/rtl/cpu_and_mem/cpu/control/forwarding_unit.sv

@@ -134,16 +134,30 @@ module forwarding_unit #(
 
   // Int -> FP capture bypass: when a load-use hazard is detected and the
   // current EX instruction is int->fp, feed MA load data directly so the
-  // FPU captures the correct operand at the stall edge.
+  // FPU captures the correct operand at the EX-entry edge.
+  // For cache-hit paths, use MA load data (same value that WB sees) rather
+  // than the cache-forward register to avoid stale-cache forwarding.
   logic int_capture_bypass_valid;
+  logic int_capture_bypass_from_cache;
+  logic int_capture_dep_match;
   logic [XLEN-1:0] int_capture_bypass_data;
+  assign int_capture_dep_match =
+      (i_from_ex_to_ma.instruction.dest_reg != 0) &&
+      (i_from_ex_to_ma.instruction.dest_reg ==
+       i_from_id_to_ex.instruction.source_reg_1);
+
+  assign int_capture_bypass_from_cache =
+      i_from_cache.cache_hit_on_load_reg &&
+      i_from_ex_to_ma.is_load_instruction &&
+      i_from_id_to_ex.is_int_to_fp &&
+      int_capture_dep_match;
+
   assign int_capture_bypass_valid =
       i_pipeline_ctrl.load_use_hazard_detected &&
       i_from_ex_to_ma.is_load_instruction &&
       i_from_id_to_ex.is_int_to_fp &&
-      (i_from_ex_to_ma.instruction.dest_reg != 0) &&
-      (i_from_ex_to_ma.instruction.dest_reg ==
-       i_from_id_to_ex.instruction.source_reg_1);
+      int_capture_dep_match ||
+      int_capture_bypass_from_cache;
 
   assign int_capture_bypass_data = i_from_ma_comb.data_loaded_from_memory;