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Add CDB arbiter module and integrate into tomasulo_wrapper
Implement priority-based CDB arbiter (Week 8) that selects one FU completion per cycle for broadcast to ROB and all RS instances. Priority order is longest-latency-first: FP_DIV > DIV > FP_MUL > MUL > FP_ADD > MEM > ALU. - New RTL: cdb_arbiter.sv (combinational fixed-priority encoder) with inline formal assertions and cover properties - New cocotb tests: 16 unit tests for priority, propagation, stress - Wrapper integration: replace i_cdb_write/i_cdb ports with i_fu_complete[NumFus]/o_cdb_grant/o_cdb, instantiate arbiter internally wired to ROB and all 6 RS instances - Update wrapper test infrastructure with fu_complete interface and backward-compat aliases for existing CDB helpers - Fix two wrapper tests that used non-allocated ROB tags for CDB broadcasts (now allocate proper producer entries first)
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formal/cdb_arbiter.sby

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[tasks]
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bmc
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cover
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[options]
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bmc: mode bmc
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bmc: depth 4
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cover: mode cover
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cover: depth 8
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[engines]
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smtbmc boolector
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[script]
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read -formal -sv riscv_pkg.sv
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read -formal -sv cdb_arbiter.sv
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prep -top cdb_arbiter
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[files]
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../hw/rtl/cpu_and_mem/cpu/riscv_pkg.sv
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../hw/rtl/cpu_and_mem/cpu/tomasulo/cdb_arbiter/cdb_arbiter.sv

formal/tomasulo_wrapper.sby

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read -sv reorder_buffer.sv
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read -sv register_alias_table.sv
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read -sv reservation_station.sv
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read -sv cdb_arbiter.sv
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read -formal -sv tomasulo_wrapper.sv
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prep -top tomasulo_wrapper
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../hw/rtl/cpu_and_mem/cpu/tomasulo/reorder_buffer/reorder_buffer.sv
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../hw/rtl/cpu_and_mem/cpu/tomasulo/register_alias_table/register_alias_table.sv
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../hw/rtl/cpu_and_mem/cpu/tomasulo/reservation_station/reservation_station.sv
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../hw/rtl/cpu_and_mem/cpu/tomasulo/cdb_arbiter/cdb_arbiter.sv
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../hw/rtl/cpu_and_mem/cpu/tomasulo/tomasulo_wrapper/tomasulo_wrapper.sv
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# CDB Arbiter
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Priority-based multiplexer that selects one functional unit completion per cycle
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for broadcast on the Common Data Bus (CDB).
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## Overview
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The CDB arbiter receives completion requests from all 7 functional units and
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grants the CDB to exactly one per cycle using fixed-priority arbitration.
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Longer-latency FUs get higher priority to avoid further stalling.
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## Interface
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| Port | Dir | Width | Description |
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|------|-----|-------|-------------|
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| `i_clk` | in | 1 | Clock (for formal only) |
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| `i_rst_n` | in | 1 | Reset (for formal only) |
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| `i_fu_complete[7]` | in | 7×81 | FU completion requests |
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| `o_cdb` | out | 84 | CDB broadcast (to RS + ROB) |
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| `o_grant[6:0]` | out | 7 | Per-FU grant signals |
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## Priority Order
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| Priority | FU Type | Latency |
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|----------|---------|---------|
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| 1 (highest) | FP_DIV | ~32-35 cycles |
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| 2 | DIV | 17 cycles |
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| 3 | FP_MUL | ~8-9 cycles |
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| 4 | MUL | 4 cycles |
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| 5 | FP_ADD | ~4-5 cycles |
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| 6 | MEM | variable |
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| 7 (lowest) | ALU | combinational |
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## Verification
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- **Formal**: BMC (depth 4) + cover (depth 8) via `formal/cdb_arbiter.sby`
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- **Cocotb**: 16 unit tests in `verif/cocotb_tests/tomasulo/cdb_arbiter/`
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## Files
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- `cdb_arbiter.sv` — RTL + formal assertions
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- `cdb_arbiter.f` — filelist
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# CDB Arbiter file list
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# Priority-based mux for FU completion → CDB broadcast
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# Package dependency
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$(ROOT)/hw/rtl/cpu_and_mem/cpu/riscv_pkg.sv
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# Module
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$(ROOT)/hw/rtl/cpu_and_mem/cpu/tomasulo/cdb_arbiter/cdb_arbiter.sv

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