stm32/i2c: Support AF irq on f4.

Signed-off-by: Damien George <[email protected]>

Author: dpgeorge

ports/stm32/i2c.c

@@ -615,7 +615,14 @@ void I2C1_EV_IRQHandler(void) {
 void I2C1_ER_IRQHandler(void) {
     MP_STATIC_ASSERT(I2C1_ER_IRQn > 0);
     IRQ_ENTER(I2C1_ER_IRQn);
-    i2c_er_irq_handler(1);
+    #if MICROPY_HW_ENABLE_HW_I2C_TARGET
+    if (i2c_target_enabled & 1) {
+        i2c_slave_ev_irq_handler(I2C1);
+    } else
+    #endif
+    {
+        i2c_er_irq_handler(1);
+    }
     IRQ_EXIT(I2C1_ER_IRQn);
 }
 #endif // defined(MICROPY_HW_I2C1_SCL)

ports/stm32/i2cslave.c

@@ -28,15 +28,29 @@
 
 #if defined(STM32F4)
 
+// The hardware triggers the following IRQs for the given scenarios:
+// - scan (0-length write):                 ADDR STOPF
+// - write of n bytes:                      ADDR RXNE*n STOPF
+// - read of n bytes:                       ADDR TXE*(n+1) AF
+// - write of n bytes then read of m bytes: ADDR RXNE*n ADDR TXE*(m+1) AF
+
 void i2c_slave_init_helper(i2c_slave_t *i2c, int addr) {
-    i2c->CR2 = I2C_CR2_ITBUFEN | I2C_CR2_ITEVTEN | 4 << I2C_CR2_FREQ_Pos;
+    i2c->CR2 = I2C_CR2_ITBUFEN | I2C_CR2_ITEVTEN | 4 << I2C_CR2_FREQ_Pos | I2C_CR2_ITERREN;
     i2c->OAR1 = 1 << 14 | addr << 1;
     i2c->OAR2 = 0;
     i2c->CR1 = I2C_CR1_ACK | I2C_CR1_PE;
 }
 
 void i2c_slave_ev_irq_handler(i2c_slave_t *i2c) {
     uint32_t sr1 = i2c->SR1;
+
+    // Clear all error flags.
+    i2c->SR1 &= ~(I2C_SR1_SMBALERT | I2C_SR1_TIMEOUT | I2C_SR1_PECERR | I2C_SR1_OVR | I2C_SR1_AF | I2C_SR1_ARLO | I2C_SR1_BERR);
+
+    if (sr1 & I2C_SR1_AF) {
+        // A NACK in TX mode, which is a stop condition.
+        i2c_slave_process_tx_end(i2c);
+    }
     if (sr1 & I2C_SR1_ADDR) {
         // Address matched
         // Read of SR1, SR2 needed to clear ADDR bit