rp2/machine_i2c_target: Use direct register access.

Signed-off-by: Damien George <[email protected]>

Author: dpgeorge

ports/rp2/machine_i2c_target.c

@@ -27,7 +27,7 @@
 // This file is never compiled standalone, it's included directly from
 // extmod/machine_i2c_target.c via MICROPY_PY_MACHINE_I2C_TARGET_INCLUDEFILE.
 
-#include "pico/i2c_slave.h"
+#include "hardware/i2c.h"
 
 // TODO: should be in a common i2c header
 #ifdef MICROPY_HW_I2C_NO_DEFAULT_PINS
@@ -75,6 +75,7 @@ typedef struct _machine_i2c_target_obj_t {
     i2c_inst_t *const i2c_inst;
     mp_hal_pin_obj_t scl;
     mp_hal_pin_obj_t sda;
+    uint8_t state;
 } machine_i2c_target_obj_t;
 
 static machine_i2c_target_data_t i2c_target_data[4];
@@ -85,41 +86,102 @@ static machine_i2c_target_obj_t machine_i2c_target_obj[] = {
 };
 
 /******************************************************************************/
-// pico-sdk bindings
+// RP2xxx hardware bindings
 
-static void i2c_target_handler(i2c_inst_t *i2c, i2c_slave_event_t event) {
+static void i2c_target_handler(i2c_inst_t *i2c) {
     unsigned int i2c_id = i2c == i2c0 ? 0 : 1;
     machine_i2c_target_obj_t *self = &machine_i2c_target_obj[i2c_id];
     machine_i2c_target_data_t *data = &i2c_target_data[i2c_id];
 
-    switch (event) {
+    // Get the interrupt status.
+    uint32_t intr_stat = i2c->hw->intr_stat;
+
+    if (intr_stat & I2C_IC_INTR_STAT_R_TX_ABRT_BITS) {
+        // Clear the TX_ABRT condition.
+        (void)i2c->hw->clr_tx_abrt;
+    }
+
+    if (intr_stat & I2C_IC_INTR_STAT_R_RX_FULL_BITS) {
         // Data from controller is available for reading.
-        case I2C_SLAVE_RECEIVE:
-            if (data->state == STATE_IDLE) {
-                machine_i2c_target_data_addr_match(data, false);
-            }
-            machine_i2c_target_data_write_request(self, data);
-            break;
+        // Mask interrupt until I2C_DATA_CMD is read from.
+        i2c->hw->intr_mask &= ~I2C_IC_INTR_MASK_M_RX_FULL_BITS;
+        if (self->state != STATE_WRITING) {
+            machine_i2c_target_data_addr_match(data, false);
+        }
+        machine_i2c_target_data_write_request(self, data);
+        self->state = STATE_WRITING;
+    }
 
+    if (intr_stat & (I2C_IC_INTR_STAT_R_RD_REQ_BITS | I2C_IC_INTR_STAT_R_RX_DONE_BITS)) {
         // Controller is requesting data.
-        case I2C_SLAVE_REQUEST: {
-            if (data->state == STATE_IDLE) {
-                machine_i2c_target_data_addr_match(data, true);
-            }
-            // i2c_write_byte_raw(i2c, 0x12);
-            // break;
-            machine_i2c_target_data_read_request(self, data);
-            break;
+        (void)i2c->hw->clr_rx_done;
+        (void)i2c->hw->clr_rd_req;
+        i2c->hw->intr_mask &= ~I2C_IC_INTR_MASK_M_RD_REQ_BITS;
+        if (self->state != STATE_READING) {
+            machine_i2c_target_data_addr_match(data, true);
         }
+        machine_i2c_target_data_read_request(self, data);
+        self->state = STATE_READING;
+    }
 
-        // Controller has sent a Stop or Restart signal.
-        case I2C_SLAVE_FINISH:
-            // TODO handle the fact this could be a restart
-            machine_i2c_target_data_restart_or_stop(data);
-            break;
+    if (intr_stat & I2C_IC_INTR_STAT_R_STOP_DET_BITS) {
+        // Controller has generated a stop condition.
+        (void)i2c->hw->clr_stop_det;
+        if (self->state == STATE_IDLE) {
+            machine_i2c_target_data_addr_match(data, false);
+        }
+        machine_i2c_target_data_restart_or_stop(data);
+        self->state = STATE_IDLE;
     }
 }
 
+static void i2c_slave_irq_handler(void) {
+    uint i2c_index = __get_current_exception() - VTABLE_FIRST_IRQ - I2C0_IRQ;
+    i2c_inst_t *i2c = i2c_get_instance(i2c_index);
+    i2c_target_handler(i2c);
+}
+
+static void i2c_slave_init(i2c_inst_t *i2c, uint16_t addr, bool addr_10bit) {
+    i2c->hw->enable = 0;
+
+    // Note: The I2C slave does clock stretching implicitly after a RD_REQ, while the Tx FIFO is empty.
+    // Clock stretching while the Rx FIFO is full is also enabled by default.
+    i2c->hw->con = I2C_IC_CON_STOP_DET_IFADDRESSED_BITS;
+    if (addr_10bit) {
+        i2c->hw->con |= I2C_IC_CON_IC_10BITADDR_SLAVE_BITS;
+    }
+    i2c->hw->sar = addr;
+    i2c->hw->tx_tl = 1;
+    i2c->hw->rx_tl = 0; // interrupt when at least 1 byte is available
+
+    // Enable interrupts.
+    i2c->hw->intr_mask =
+        I2C_IC_INTR_MASK_M_STOP_DET_BITS
+        | I2C_IC_INTR_MASK_M_RX_DONE_BITS
+        | I2C_IC_INTR_MASK_M_TX_ABRT_BITS
+        | I2C_IC_INTR_MASK_M_RD_REQ_BITS
+        | I2C_IC_INTR_MASK_M_RX_FULL_BITS
+    ;
+
+    i2c->hw->enable = 1;
+
+    // Enable interrupt for current core.
+    uint i2c_index = i2c_hw_index(i2c);
+    uint num = I2C0_IRQ + i2c_index;
+    irq_set_exclusive_handler(num, i2c_slave_irq_handler);
+    irq_set_enabled(num, true);
+}
+
+static void i2c_slave_deinit(i2c_inst_t *i2c) {
+    uint i2c_index = i2c_hw_index(i2c);
+    uint num = I2C0_IRQ + i2c_index;
+    irq_set_enabled(num, false);
+    irq_remove_handler(num, i2c_slave_irq_handler);
+
+    i2c->hw->intr_mask = 0;
+    i2c->hw->enable = 0;
+}
+
 /******************************************************************************/
 // I2CTarget port implementation
 
@@ -131,16 +193,29 @@ static void mp_machine_i2c_target_event_callback(machine_i2c_target_irq_obj_t *i
 }
 
 static mp_int_t mp_machine_i2c_target_read_bytes(machine_i2c_target_obj_t *self, size_t len, uint8_t *buf) {
-    i2c_hw_t *i2c_hw = i2c_get_hw(self->i2c_inst);
+    i2c_hw_t *i2c_hw = self->i2c_inst->hw;
+
+    // Read from the RX FIFO.
     mp_int_t i = 0;
-    while (i < len && i2c_hw->status & I2C_IC_STATUS_RFNE_BITS) {
-        buf[i++] = i2c_read_byte_raw(self->i2c_inst);
+    while (i < len && (i2c_hw->status & I2C_IC_STATUS_RFNE_BITS)) {
+        buf[i++] = i2c_hw->data_cmd;
     }
+
+    // Re-enable RX_FULL interrupt.
+    i2c_hw->intr_mask |= I2C_IC_INTR_MASK_M_RX_FULL_BITS;
+
     return i;
 }
 
 static mp_int_t mp_machine_i2c_target_write_bytes(machine_i2c_target_obj_t *self, size_t len, const uint8_t *buf) {
-    i2c_write_byte_raw(self->i2c_inst, buf[0]);
+    i2c_hw_t *i2c_hw = self->i2c_inst->hw;
+
+    // Write to the TX FIFO.
+    i2c_hw->data_cmd = buf[0];
+
+    // Re-enable RD_REQ interrupt.
+    i2c_hw->intr_mask |= I2C_IC_INTR_MASK_M_RD_REQ_BITS;
+
     return 1;
 }
 
@@ -179,6 +254,7 @@ static mp_obj_t mp_machine_i2c_target_make_new(const mp_obj_type_t *type, size_t
     machine_i2c_target_obj_t *self = &machine_i2c_target_obj[i2c_id];
 
     // Initialise data.
+    self->state = STATE_IDLE;
     MP_STATE_PORT(i2c_target_mem_obj)[i2c_id] = args[ARG_mem].u_obj;
     machine_i2c_target_data_t *data = &i2c_target_data[i2c_id];
     machine_i2c_target_data_init(data, args[ARG_mem].u_obj, args[ARG_mem_addrsize].u_int);
@@ -201,7 +277,7 @@ static mp_obj_t mp_machine_i2c_target_make_new(const mp_obj_type_t *type, size_t
 
     // Initialise the I2C target.
     // TODO: don't reinitialize if no arguments given.
-    i2c_slave_init(self->i2c_inst, args[ARG_addr].u_int, i2c_target_handler);
+    i2c_slave_init(self->i2c_inst, args[ARG_addr].u_int, args[ARG_addrsize].u_int == 10);
     gpio_set_function(self->scl, GPIO_FUNC_I2C);
     gpio_set_function(self->sda, GPIO_FUNC_I2C);
     gpio_set_pulls(self->scl, true, 0);