update for chipsalliance/chisel#1944

Author: sequencer

src/main/scala/chiseltest/legacy/backends/verilator/Utils.scala

@@ -59,7 +59,6 @@ private[chiseltest] object getChiselNodes {
       case m: DefModule =>
         m.commands.flatMap {
           case x:   DefReg => flatten(x.id)
-          case x:   DefRegInit => flatten(x.id)
           case mem: DefMemory =>
             mem.t match {
               case _: Element => Seq(mem.id)