@@ -108,10 +108,10 @@ vlsi.inputs:
108108 ilms : list[dict[str, str]]
109109
110110 # Multi-mode multi-corner setups, overrides supplies
111- mmmc_corners : list[dict[str, str ]]
111+ mmmc_corners : list[dict[str, Any ]]
112112
113113 # Clock ports of the top-level module.
114- clocks : list[dict[str, str ]]
114+ clocks : list[dict[str, Any ]]
115115
116116 # Default output pin load capacitance.
117117 default_output_load : int
@@ -120,7 +120,7 @@ vlsi.inputs:
120120 output_loads : list[dict[str, str]]
121121
122122 # List of delay constraints.
123- delays : list[dict[str, str ]]
123+ delays : list[dict[str, Any ]]
124124
125125 # List of custom sdc constraints to use. (List[str])
126126 custom_sdc_constraints : list[str]
@@ -161,7 +161,7 @@ vlsi.inputs:
161161 # cell (str) - Name of the default bump cell
162162 cell : str
163163 # assignments - List of BumpAssignment structs. You must specify one of name or no_connect.
164- assignments : list[dict[str, str ]]
164+ assignments : list[dict[str, Any ]]
165165
166166 # Naming scheme for the bumps' actual physical pin designators
167167 # type: str
@@ -174,10 +174,10 @@ vlsi.inputs:
174174 generate_mode : str
175175
176176 # List of PinAssignment Structs.
177- assignments : list[dict[str, str ]]
177+ assignments : list[dict[str, Any ]]
178178
179179 # List of decap constraints (DecapConstraint struct).
180- decaps : list[dict[str, str ]]
180+ decaps : list[dict[str, Any ]]
181181
182182 # SVG visualization of placement constraints and bumps for the current hierarchical module.
183183 visualization :
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