[Synth] Add LogicNetwork flat IR representation for CutRewriter

Add mockturtle-style flat logic network representation for efficient
cut enumeration and truth table computation:

- LogicEdge: 32-bit value encoding node index and inversion in LSB
- LogicNetworkGate: Gate struct with Kind enum and up to 3 edges
- LogicNetwork: Value numbering with indices 0/1 reserved for constants

The LogicNetwork is now built during CutEnumerator::enumerateCuts()
and provides O(1) gate lookup by index. This is the foundation for
converting Cut.inputs from Value pointers to integer indices.

Author: uenoku

include/circt/Dialect/Synth/Transforms/CutRewriter.h

@@ -356,10 +356,15 @@ LogicalResult AIGERRunner::runSolver(hw::HWModuleOp module, StringRef inputPath,
     commandArgs.push_back(processedArg);
 
   // Execute the solver
+  auto startTime = std::chrono::high_resolution_clock::now();
   int executionResult = llvm::sys::ExecuteAndWait(
       solverProgram.get(), commandArgs,
       /*Env=*/std::nullopt, /*Redirects=*/{},
       /*SecondsToWait=*/0, /*MemoryLimit=*/0, &executionError);
+  auto endTime = std::chrono::high_resolution_clock::now();
+  std::chrono::duration<double> elapsedSeconds = endTime - startTime;
+  llvm::dbgs() << "Solver execution time: " << elapsedSeconds.count()
+               << " seconds\n";
 
   // Check for execution failure
   if (executionResult != 0)