Is there only one frequency for clocks all the time?

[Z-KN]

DRAMsim is cycle-accurate, and I learned how it advances the clock clk_. But in terms of real-word latency on the wall clock, how do you measure that? If the clk_ has a constant frequency, that is not an issue; while if DRAM has clock domains of different frequencies, how could you obtain the overall latency? Is that the case? Is it reflected in the code?

[theatomb]

DRAMsim3 assumes a single clock domain