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amaanqamaanq
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feat!: update RISC-V to 5.1.0
1 parent 515d513 commit 20ad653

20 files changed

+15424
-1073
lines changed

‎qemu/target/riscv/cpu.c‎

Lines changed: 93 additions & 66 deletions
Original file line numberDiff line numberDiff line change
@@ -30,22 +30,20 @@
3030

3131
// static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
3232

33-
const char * const riscv_int_regnames[] = {
34-
"x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
35-
"x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
36-
"x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4",
37-
"x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
38-
"x28/t3", "x29/t4", "x30/t5", "x31/t6"
39-
};
40-
41-
const char * const riscv_fpr_regnames[] = {
42-
"f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5",
43-
"f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1",
44-
"f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7",
45-
"f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7",
46-
"f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
47-
"f30/ft10", "f31/ft11"
48-
};
33+
const char *const riscv_int_regnames[] = {
34+
"x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
35+
"x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
36+
"x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4",
37+
"x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
38+
"x28/t3", "x29/t4", "x30/t5", "x31/t6"};
39+
40+
const char *const riscv_fpr_regnames[] = {
41+
"f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5",
42+
"f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1",
43+
"f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7",
44+
"f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7",
45+
"f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
46+
"f30/ft10", "f31/ft11"};
4947

5048
static void set_misa(CPURISCVState *env, target_ulong misa)
5149
{
@@ -57,6 +55,11 @@ static void set_priv_version(CPURISCVState *env, int priv_ver)
5755
env->priv_ver = priv_ver;
5856
}
5957

58+
static void set_vext_version(CPURISCVState *env, int vext_ver)
59+
{
60+
env->vext_ver = vext_ver;
61+
}
62+
6063
static void set_feature(CPURISCVState *env, int feature)
6164
{
6265
env->features |= (1ULL << feature);
@@ -75,65 +78,48 @@ static void riscv_any_cpu_init(CPUState *obj)
7578
set_resetvec(env, DEFAULT_RSTVEC);
7679
}
7780

78-
#if defined(TARGET_RISCV32)
79-
// rv32
80-
static void riscv_base32_cpu_init(CPUState *obj)
81+
static void riscv_base_cpu_init(CPUState *obj)
8182
{
8283
CPURISCVState *env = &RISCV_CPU(obj)->env;
8384
/* We set this in the realise function */
8485
set_misa(env, 0);
86+
set_resetvec(env, DEFAULT_RSTVEC);
8587
}
8688

87-
// sifive-u34
88-
static void rv32gcsu_priv1_10_0_cpu_init(CPUState *obj)
89+
static void rvxx_sifive_u_cpu_init(CPUState *obj)
8990
{
9091
CPURISCVState *env = &RISCV_CPU(obj)->env;
91-
set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
92+
set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
9293
set_priv_version(env, PRIV_VERSION_1_10_0);
93-
set_resetvec(env, DEFAULT_RSTVEC);
94-
set_feature(env, RISCV_FEATURE_MMU);
95-
set_feature(env, RISCV_FEATURE_PMP);
94+
set_resetvec(env, 0x1004);
9695
}
9796

98-
// sifive-e31
99-
static void rv32imacu_nommu_cpu_init(CPUState *obj)
97+
static void rvxx_sifive_e_cpu_init(CPUState *obj)
10098
{
10199
CPURISCVState *env = &RISCV_CPU(obj)->env;
102-
set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
100+
set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU);
103101
set_priv_version(env, PRIV_VERSION_1_10_0);
104-
set_resetvec(env, DEFAULT_RSTVEC);
105-
set_feature(env, RISCV_FEATURE_PMP);
102+
set_resetvec(env, 0x1004);
106103
}
107104

108-
#elif defined(TARGET_RISCV64)
109-
// rv64
110-
static void riscv_base64_cpu_init(CPUState *obj)
111-
{
112-
CPURISCVState *env = &RISCV_CPU(obj)->env;
113-
/* We set this in the realise function */
114-
set_misa(env, 0);
115-
}
105+
#if defined(TARGET_RISCV32)
116106

117-
// sifive-u54
118-
static void rv64gcsu_priv1_10_0_cpu_init(CPUState *obj)
107+
static void rv32_ibex_cpu_init(CPUState *obj)
119108
{
120109
CPURISCVState *env = &RISCV_CPU(obj)->env;
121-
set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
110+
set_misa(env, RV32 | RVI | RVM | RVC | RVU);
122111
set_priv_version(env, PRIV_VERSION_1_10_0);
123-
set_resetvec(env, DEFAULT_RSTVEC);
124-
set_feature(env, RISCV_FEATURE_MMU);
125-
set_feature(env, RISCV_FEATURE_PMP);
112+
set_resetvec(env, 0x8090);
126113
}
127114

128-
// sifive-e51
129-
static void rv64imacu_nommu_cpu_init(CPUState *obj)
115+
static void rv32_imafcu_nommu_cpu_init(CPUState *obj)
130116
{
131117
CPURISCVState *env = &RISCV_CPU(obj)->env;
132-
set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
118+
set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU);
133119
set_priv_version(env, PRIV_VERSION_1_10_0);
134120
set_resetvec(env, DEFAULT_RSTVEC);
135-
set_feature(env, RISCV_FEATURE_PMP);
136121
}
122+
137123
#endif
138124

139125
static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
@@ -192,6 +178,7 @@ static void riscv_cpu_realize(struct uc_struct *uc, CPUState *dev)
192178
RISCVCPU *cpu = RISCV_CPU(dev);
193179
CPURISCVState *env = &cpu->env;
194180
int priv_version = PRIV_VERSION_1_11_0;
181+
int vext_version = VEXT_VERSION_0_07_1;
195182
target_ulong target_misa = 0;
196183

197184
cpu_exec_realizefn(cs);
@@ -201,16 +188,15 @@ static void riscv_cpu_realize(struct uc_struct *uc, CPUState *dev)
201188
priv_version = PRIV_VERSION_1_11_0;
202189
} else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
203190
priv_version = PRIV_VERSION_1_10_0;
204-
} else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.9.1")) {
205-
priv_version = PRIV_VERSION_1_09_1;
206191
} else {
207-
// error_setg(errp, "Unsupported privilege spec version '%s'", cpu->cfg.priv_spec);
192+
// error_setg(errp, "Unsupported privilege spec version '%s'",
193+
// cpu->cfg.priv_spec);
208194
return;
209195
}
210196
}
211197

212198
set_priv_version(env, priv_version);
213-
set_resetvec(env, DEFAULT_RSTVEC);
199+
set_vext_version(env, vext_version);
214200

215201
if (cpu->cfg.mmu) {
216202
set_feature(env, RISCV_FEATURE_MMU);
@@ -224,7 +210,7 @@ static void riscv_cpu_realize(struct uc_struct *uc, CPUState *dev)
224210
if (!env->misa) {
225211
/* Do some ISA extension error checking */
226212
if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
227-
//error_setg(errp, "I and E extensions are incompatible");
213+
// error_setg(errp, "I and E extensions are incompatible");
228214
return;
229215
}
230216

@@ -233,8 +219,9 @@ static void riscv_cpu_realize(struct uc_struct *uc, CPUState *dev)
233219
return;
234220
}
235221

236-
if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
237-
cpu->cfg.ext_a & cpu->cfg.ext_f & cpu->cfg.ext_d)) {
222+
if (cpu->cfg.ext_g &&
223+
!(cpu->cfg.ext_i & cpu->cfg.ext_m & cpu->cfg.ext_a &
224+
cpu->cfg.ext_f & cpu->cfg.ext_d)) {
238225
// warn_report("Setting G will also set IMAFD");
239226
cpu->cfg.ext_i = true;
240227
cpu->cfg.ext_m = true;
@@ -274,6 +261,45 @@ static void riscv_cpu_realize(struct uc_struct *uc, CPUState *dev)
274261
if (cpu->cfg.ext_h) {
275262
target_misa |= RVH;
276263
}
264+
if (cpu->cfg.ext_v) {
265+
target_misa |= RVV;
266+
if (!is_power_of_2(cpu->cfg.vlen)) {
267+
// error_setg(errp,
268+
// "Vector extension VLEN must be power of 2");
269+
return;
270+
}
271+
if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) {
272+
// error_setg(errp,
273+
// "Vector extension implementation only supports VLEN "
274+
// "in the range [128, %d]", RV_VLEN_MAX);
275+
return;
276+
}
277+
if (!is_power_of_2(cpu->cfg.elen)) {
278+
// error_setg(errp,
279+
// "Vector extension ELEN must be power of 2");
280+
return;
281+
}
282+
if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) {
283+
// error_setg(errp,
284+
// "Vector extension implementation only supports ELEN "
285+
// "in the range [8, 64]");
286+
return;
287+
}
288+
if (cpu->cfg.vext_spec) {
289+
if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) {
290+
vext_version = VEXT_VERSION_0_07_1;
291+
} else {
292+
// error_setg(errp,
293+
// "Unsupported vector spec version '%s'",
294+
// cpu->cfg.vext_spec);
295+
return;
296+
}
297+
} else {
298+
// qemu_log("vector verison is not specified, "
299+
// "use the default value v0.7.1\n");
300+
}
301+
set_vext_version(env, vext_version);
302+
}
277303

278304
set_misa(env, RVXLEN | target_misa);
279305
}
@@ -316,16 +342,17 @@ typedef struct CPUModelInfo {
316342
} CPUModelInfo;
317343

318344
static const CPUModelInfo cpu_models[] = {
319-
{TYPE_RISCV_CPU_ANY, riscv_any_cpu_init},
320-
#ifdef TARGET_RISCV32
321-
{TYPE_RISCV_CPU_BASE32, riscv_base32_cpu_init},
322-
{TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init},
323-
{TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init},
324-
#endif
325-
#ifdef TARGET_RISCV64
326-
{TYPE_RISCV_CPU_BASE64, riscv_base64_cpu_init},
327-
{TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init},
328-
{TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init},
345+
{TYPE_RISCV_CPU_ANY, riscv_any_cpu_init},
346+
#if defined(TARGET_RISCV32)
347+
{TYPE_RISCV_CPU_BASE32, riscv_base_cpu_init},
348+
{TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init},
349+
{TYPE_RISCV_CPU_SIFIVE_E31, rvxx_sifive_e_cpu_init},
350+
{TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init},
351+
{TYPE_RISCV_CPU_SIFIVE_U34, rvxx_sifive_u_cpu_init},
352+
#elif defined(TARGET_RISCV64)
353+
{TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init},
354+
{TYPE_RISCV_CPU_SIFIVE_E51, rvxx_sifive_e_cpu_init},
355+
{TYPE_RISCV_CPU_SIFIVE_U54, rvxx_sifive_u_cpu_init},
329356
#endif
330357
};
331358

@@ -339,7 +366,7 @@ RISCVCPU *cpu_riscv_init(struct uc_struct *uc)
339366
if (cpu == NULL) {
340367
return NULL;
341368
}
342-
memset((void*)cpu, 0, sizeof(*cpu));
369+
memset((void *)cpu, 0, sizeof(*cpu));
343370

344371
#ifdef TARGET_RISCV32
345372
if (uc->cpu_model == INT_MAX) {

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