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feat!: update i386 to 5.1.0
1 parent 52ac072 commit 220332e

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8 files changed

+179
-84
lines changed

8 files changed

+179
-84
lines changed

‎qemu/target/i386/cpu.c‎

Lines changed: 83 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -852,10 +852,10 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
852852
.type = CPUID_FEATURE_WORD,
853853
.feat_names = {
854854
NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
855-
NULL, NULL, NULL, NULL,
856-
NULL, NULL, "md-clear", NULL,
857-
NULL, NULL, NULL, NULL,
858-
NULL, NULL, NULL /* pconfig */, NULL,
855+
"fsrm", NULL, NULL, NULL,
856+
"avx512-vp2intersect", NULL, "md-clear", NULL,
857+
NULL, NULL, "serialize", NULL,
858+
"tsx-ldtrk", NULL, NULL /* pconfig */, NULL,
859859
NULL, NULL, NULL, NULL,
860860
NULL, NULL, "spec-ctrl", "stibp",
861861
NULL, "arch-capabilities", "core-capability", "ssbd",
@@ -1001,6 +1001,22 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
10011001
.index = MSR_IA32_CORE_CAPABILITY,
10021002
},
10031003
},
1004+
[FEAT_PERF_CAPABILITIES] = {
1005+
.type = MSR_FEATURE_WORD,
1006+
.feat_names = {
1007+
NULL, NULL, NULL, NULL,
1008+
NULL, NULL, NULL, NULL,
1009+
NULL, NULL, NULL, NULL,
1010+
NULL, "full-width-write", NULL, NULL,
1011+
NULL, NULL, NULL, NULL,
1012+
NULL, NULL, NULL, NULL,
1013+
NULL, NULL, NULL, NULL,
1014+
NULL, NULL, NULL, NULL,
1015+
},
1016+
.msr = {
1017+
.index = MSR_IA32_PERF_CAPABILITIES,
1018+
},
1019+
},
10041020

10051021
[FEAT_VMX_PROCBASED_CTLS] = {
10061022
.type = MSR_FEATURE_WORD,
@@ -2722,6 +2738,13 @@ static X86CPUDefinition builtin_x86_defs[] = {
27222738
{ NULL /* end of list */ }
27232739
}
27242740
},
2741+
{
2742+
.version = 4,
2743+
.props = (PropValue[]) {
2744+
{ "vmx-eptp-switching", "on" },
2745+
{ /* end of list */ }
2746+
}
2747+
},
27252748
{ 0 /* end of list */ }
27262749
}
27272750
},
@@ -2827,6 +2850,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
28272850
.versions = (X86CPUVersionDefinition[]) {
28282851
{ .version = 1 },
28292852
{ .version = 2,
2853+
.note = "ARCH_CAPABILITIES",
28302854
.props = (PropValue[]) {
28312855
{ "arch-capabilities", "on" },
28322856
{ "rdctl-no", "on" },
@@ -2838,12 +2862,20 @@ static X86CPUDefinition builtin_x86_defs[] = {
28382862
},
28392863
{ .version = 3,
28402864
.alias = "Cascadelake-Server-noTSX",
2865+
.note = "ARCH_CAPABILITIES, no TSX",
28412866
.props = (PropValue[]) {
28422867
{ "hle", "off" },
28432868
{ "rtm", "off" },
28442869
{ NULL /* end of list */ }
28452870
},
28462871
},
2872+
{ .version = 4,
2873+
.note = "ARCH_CAPABILITIES, no TSX",
2874+
.props = (PropValue[]) {
2875+
{ "vmx-eptp-switching", "on" },
2876+
{ /* end of list */ }
2877+
},
2878+
},
28472879
{ 0 /* end of list */ }
28482880
}
28492881
},
@@ -3059,6 +3091,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
30593091
{ .version = 1 },
30603092
{
30613093
.version = 2,
3094+
.note = "no TSX",
30623095
.alias = "Icelake-Client-noTSX",
30633096
.props = (PropValue[]) {
30643097
{ "hle", "off" },
@@ -3196,6 +3229,20 @@ static X86CPUDefinition builtin_x86_defs[] = {
31963229
{ NULL /* end of list */ }
31973230
},
31983231
},
3232+
{
3233+
.version = 4,
3234+
.props = (PropValue[]) {
3235+
{ "sha-ni", "on" },
3236+
{ "avx512ifma", "on" },
3237+
{ "rdpid", "on" },
3238+
{ "fsrm", "on" },
3239+
{ "vmx-rdseed-exit", "on" },
3240+
{ "vmx-pml", "on" },
3241+
{ "vmx-eptp-switching", "on" },
3242+
{ "model", "106" },
3243+
{ /* end of list */ }
3244+
},
3245+
},
31993246
{ 0 /* end of list */ }
32003247
}
32013248
},
@@ -3296,6 +3343,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
32963343
{ .version = 1 },
32973344
{
32983345
.version = 2,
3346+
.note = "no MPX, no MONITOR",
32993347
.props = (PropValue[]) {
33003348
{ "monitor", "off" },
33013349
{ "mpx", "off" },
@@ -3828,16 +3876,6 @@ static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask,
38283876
}
38293877
}
38303878

3831-
/* Convert all '_' in a feature string option name to '-', to make feature
3832-
* name conform to QOM property naming rule, which uses '-' instead of '_'.
3833-
*/
3834-
static inline void feat2prop(char *s)
3835-
{
3836-
while ((s = strchr(s, '_'))) {
3837-
*s = '-';
3838-
}
3839-
}
3840-
38413879
static void x86_cpu_filter_features(X86CPU *cpu, bool verbose);
38423880

38433881
static uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
@@ -3888,6 +3926,13 @@ static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model)
38883926
}
38893927

38903928
x86_cpuid_set_vendor(cpu, def->vendor);
3929+
3930+
/*
3931+
* Properties in versioned CPU model are not user specified features.
3932+
* We can simply clear env->user_features here since it will be filled later
3933+
* in x86_cpu_expand_features() based on plus_features and minus_features.
3934+
*/
3935+
memset(&env->user_features, 0, sizeof(env->user_features));
38913936
}
38923937

38933938
void cpu_clear_apic_feature(CPUX86State *env)
@@ -4042,6 +4087,9 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
40424087
*ebx |= (cs->nr_cores * cs->nr_threads) << 16;
40434088
*edx |= CPUID_HT;
40444089
}
4090+
if (!cpu->enable_pmu) {
4091+
*ecx &= ~CPUID_EXT_PDCM;
4092+
}
40454093
break;
40464094
case 2:
40474095
/* cache info: needed for Pentium Pro compatibility */
@@ -4330,9 +4378,9 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
43304378
host_cpuid(index, 0, eax, ebx, ecx, edx);
43314379
break;
43324380
}
4333-
*eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
4381+
*eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) |
43344382
(L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
4335-
*ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
4383+
*ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) |
43364384
(L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
43374385
*ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache);
43384386
*edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache);
@@ -4343,13 +4391,13 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
43434391
host_cpuid(index, 0, eax, ebx, ecx, edx);
43444392
break;
43454393
}
4346-
*eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
4394+
*eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) |
43474395
(L2_DTLB_2M_ENTRIES << 16) | \
4348-
(AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
4396+
(AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) |
43494397
(L2_ITLB_2M_ENTRIES);
4350-
*ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
4398+
*ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) |
43514399
(L2_DTLB_4K_ENTRIES << 16) | \
4352-
(AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
4400+
(AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) |
43534401
(L2_ITLB_4K_ENTRIES);
43544402
encode_cache_cpuid80000006(env->cache_info_amd.l2_cache,
43554403
cpu->enable_l3_cache ?
@@ -4376,11 +4424,20 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
43764424
*eax = cpu->phys_bits;
43774425
}
43784426
*ebx = env->features[FEAT_8000_0008_EBX];
4379-
*ecx = 0;
4380-
*edx = 0;
43814427
if (cs->nr_cores * cs->nr_threads > 1) {
4382-
*ecx |= (cs->nr_cores * cs->nr_threads) - 1;
4428+
/*
4429+
* Bits 15:12 is "The number of bits in the initial
4430+
* Core::X86::Apic::ApicId[ApicId] value that indicate
4431+
* thread ID within a package". This is already stored at
4432+
* CPUX86State::pkg_offset.
4433+
* Bits 7:0 is "The number of threads in the package is NC+1"
4434+
*/
4435+
*ecx = (env->pkg_offset << 12) |
4436+
((cs->nr_cores * cs->nr_threads) - 1);
4437+
} else {
4438+
*ecx = 0;
43834439
}
4440+
*edx = 0;
43844441
break;
43854442
case 0x8000000A:
43864443
if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
@@ -4478,6 +4535,7 @@ static void x86_cpu_reset(CPUState *dev)
44784535
/* init to reset state */
44794536

44804537
env->hflags2 |= HF2_GIF_MASK;
4538+
env->hflags &= ~HF_GUEST_MASK;
44814539

44824540
cpu_x86_update_cr0(env, 0x60000010);
44834541
env->a20_mask = ~0x0;
@@ -4707,7 +4765,7 @@ static void x86_cpu_expand_features(X86CPU *cpu)
47074765
*/
47084766
env->features[w] |=
47094767
x86_cpu_get_supported_feature_word(w, cpu->migratable) &
4710-
~env->user_features[w] & \
4768+
~env->user_features[w] &
47114769
~feature_word_info[w].no_autoenable_flags;
47124770
}
47134771
}
@@ -4740,7 +4798,7 @@ static void x86_cpu_expand_features(X86CPU *cpu)
47404798
// TODO: Add a warning?
47414799
// mark_unavailable_features(cpu, FEAT_7_0_EBX,
47424800
// CPUID_7_0_EBX_INTEL_PT,
4743-
// "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,+intel-pt,level=0x14\"");
4801+
// "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,+intel-pt,min-level=0x14\"");
47444802
}
47454803
}
47464804

‎qemu/target/i386/cpu.h‎

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -352,6 +352,8 @@ typedef enum X86Seg {
352352
#define MSR_IA32_ARCH_CAPABILITIES 0x10a
353353
#define ARCH_CAP_TSX_CTRL_MSR (1<<7)
354354

355+
#define MSR_IA32_PERF_CAPABILITIES 0x345
356+
355357
#define MSR_IA32_TSX_CTRL 0x122
356358
#define MSR_IA32_TSCDEADLINE 0x6e0
357359

@@ -525,6 +527,7 @@ typedef enum FeatureWord {
525527
FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */
526528
FEAT_ARCH_CAPABILITIES,
527529
FEAT_CORE_CAPABILITY,
530+
FEAT_PERF_CAPABILITIES,
528531
FEAT_VMX_PROCBASED_CTLS,
529532
FEAT_VMX_SECONDARY_CTLS,
530533
FEAT_VMX_PINBASED_CTLS,
@@ -768,6 +771,14 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
768771
#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2)
769772
/* AVX512 Multiply Accumulation Single Precision */
770773
#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3)
774+
/* Fast Short Rep Mov */
775+
#define CPUID_7_0_EDX_FSRM (1U << 4)
776+
/* AVX512 Vector Pair Intersection to a Pair of Mask Registers */
777+
#define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8)
778+
/* SERIALIZE instruction */
779+
#define CPUID_7_0_EDX_SERIALIZE (1U << 14)
780+
/* TSX Suspend Load Address Tracking instruction */
781+
#define CPUID_7_0_EDX_TSX_LDTRK (1U << 16)
771782
/* Speculation Control */
772783
#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
773784
/* Single Thread Indirect Branch Predictors */
@@ -1571,6 +1582,7 @@ typedef struct CPUX86State {
15711582
bool tsc_valid;
15721583
int64_t tsc_khz;
15731584
int64_t user_tsc_khz; /* for sanity check only */
1585+
uint64_t apic_bus_freq;
15741586

15751587
uint64_t mcg_cap;
15761588
uint64_t mcg_ctl;
@@ -2043,6 +2055,11 @@ static inline bool cpu_has_vmx(CPUX86State *env)
20432055
return env->features[FEAT_1_ECX] & CPUID_EXT_VMX;
20442056
}
20452057

2058+
static inline bool cpu_has_svm(CPUX86State *env)
2059+
{
2060+
return env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM;
2061+
}
2062+
20462063
/*
20472064
* In order for a vCPU to enter VMX operation it must have CR4.VMXE set.
20482065
* Since it was set, CR4.VMXE must remain set as long as vCPU is in
@@ -2068,6 +2085,7 @@ static inline bool cpu_vmx_maybe_enabled(CPUX86State *env)
20682085
/* fpu_helper.c */
20692086
void update_fp_status(CPUX86State *env);
20702087
void update_mxcsr_status(CPUX86State *env);
2088+
void update_mxcsr_from_sse_status(CPUX86State *env);
20712089

20722090
static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr)
20732091
{

‎qemu/target/i386/excp_helper.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -261,8 +261,8 @@ static hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType access_type,
261261
}
262262
ptep = pde | PG_NX_MASK;
263263

264-
/* if PSE bit is set, then we use a 4MB page */
265-
if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
264+
/* if host cr4 PSE bit is set, then we use a 4MB page */
265+
if ((pde & PG_PSE_MASK) && (env->nested_pg_mode & SVM_NPT_PSE)) {
266266
page_size = 4096 * 1024;
267267
pte_addr = pde_addr;
268268

‎qemu/target/i386/helper.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -210,6 +210,7 @@ DEF_HELPER_FLAGS_2(pext, TCG_CALL_NO_RWG_SE, tl, tl, tl)
210210
/* MMX/SSE */
211211

212212
DEF_HELPER_2(ldmxcsr, void, env, i32)
213+
DEF_HELPER_1(update_mxcsr, void, env)
213214
DEF_HELPER_1(enter_mmx, void, env)
214215
DEF_HELPER_1(emms, void, env)
215216
DEF_HELPER_3(movq, void, env, ptr, ptr)

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