feat!: update bindings

amaanq · amaanq · commit 4595bde5a4ec · 2025-04-06T00:34:48.000-04:00
diff --git a/bindings/dotnet/UnicornEngine/Const/Mips.fs b/bindings/dotnet/UnicornEngine/Const/Mips.fs
@@ -41,8 +41,10 @@ module Mips =
     let UC_CPU_MIPS64_I6500 = 9
     let UC_CPU_MIPS64_LOONGSON_2E = 10
     let UC_CPU_MIPS64_LOONGSON_2F = 11
-    let UC_CPU_MIPS64_MIPS64DSPR2 = 12
-    let UC_CPU_MIPS64_ENDING = 13
+    let UC_CPU_MIPS64_LOONGSON_3A1000 = 12
+    let UC_CPU_MIPS64_LOONGSON_3A4000 = 13
+    let UC_CPU_MIPS64_MIPS64DSPR2 = 14
+    let UC_CPU_MIPS64_ENDING = 15
 
     // MIPS registers
 
diff --git a/bindings/dotnet/UnicornEngine/Const/Riscv.fs b/bindings/dotnet/UnicornEngine/Const/Riscv.fs
@@ -10,15 +10,17 @@ module Riscv =
     // RISCV32 CPU
 
     let UC_CPU_RISCV32_ANY = 0
-    let UC_CPU_RISCV32_BASE32 = 1
-    let UC_CPU_RISCV32_SIFIVE_E31 = 2
-    let UC_CPU_RISCV32_SIFIVE_U34 = 3
-    let UC_CPU_RISCV32_ENDING = 4
+    let UC_CPU_RISCV32_BASE = 1
+    let UC_CPU_RISCV32_IBEX = 2
+    let UC_CPU_RISCV32_SIFIVE_E31 = 3
+    let UC_CPU_RISCV32_SIFIVE_E34 = 4
+    let UC_CPU_RISCV32_SIFIVE_U34 = 5
+    let UC_CPU_RISCV32_ENDING = 6
 
     // RISCV64 CPU
 
     let UC_CPU_RISCV64_ANY = 0
-    let UC_CPU_RISCV64_BASE64 = 1
+    let UC_CPU_RISCV64_BASE = 1
     let UC_CPU_RISCV64_SIFIVE_E51 = 2
     let UC_CPU_RISCV64_SIFIVE_U54 = 3
     let UC_CPU_RISCV64_ENDING = 4
diff --git a/bindings/go/unicorn/mips_const.go b/bindings/go/unicorn/mips_const.go
@@ -36,8 +36,10 @@ const (
 	CPU_MIPS64_I6500 = 9
 	CPU_MIPS64_LOONGSON_2E = 10
 	CPU_MIPS64_LOONGSON_2F = 11
-	CPU_MIPS64_MIPS64DSPR2 = 12
-	CPU_MIPS64_ENDING = 13
+	CPU_MIPS64_LOONGSON_3A1000 = 12
+	CPU_MIPS64_LOONGSON_3A4000 = 13
+	CPU_MIPS64_MIPS64DSPR2 = 14
+	CPU_MIPS64_ENDING = 15
 
 // MIPS registers
 
diff --git a/bindings/go/unicorn/riscv_const.go b/bindings/go/unicorn/riscv_const.go
@@ -5,15 +5,17 @@ const (
 // RISCV32 CPU
 
 	CPU_RISCV32_ANY = 0
-	CPU_RISCV32_BASE32 = 1
-	CPU_RISCV32_SIFIVE_E31 = 2
-	CPU_RISCV32_SIFIVE_U34 = 3
-	CPU_RISCV32_ENDING = 4
+	CPU_RISCV32_BASE = 1
+	CPU_RISCV32_IBEX = 2
+	CPU_RISCV32_SIFIVE_E31 = 3
+	CPU_RISCV32_SIFIVE_E34 = 4
+	CPU_RISCV32_SIFIVE_U34 = 5
+	CPU_RISCV32_ENDING = 6
 
 // RISCV64 CPU
 
 	CPU_RISCV64_ANY = 0
-	CPU_RISCV64_BASE64 = 1
+	CPU_RISCV64_BASE = 1
 	CPU_RISCV64_SIFIVE_E51 = 2
 	CPU_RISCV64_SIFIVE_U54 = 3
 	CPU_RISCV64_ENDING = 4
diff --git a/bindings/java/src/main/java/unicorn/MipsConst.java b/bindings/java/src/main/java/unicorn/MipsConst.java
@@ -38,8 +38,10 @@ public interface MipsConst {
     public static final int UC_CPU_MIPS64_I6500 = 9;
     public static final int UC_CPU_MIPS64_LOONGSON_2E = 10;
     public static final int UC_CPU_MIPS64_LOONGSON_2F = 11;
-    public static final int UC_CPU_MIPS64_MIPS64DSPR2 = 12;
-    public static final int UC_CPU_MIPS64_ENDING = 13;
+    public static final int UC_CPU_MIPS64_LOONGSON_3A1000 = 12;
+    public static final int UC_CPU_MIPS64_LOONGSON_3A4000 = 13;
+    public static final int UC_CPU_MIPS64_MIPS64DSPR2 = 14;
+    public static final int UC_CPU_MIPS64_ENDING = 15;
 
     // MIPS registers
 
diff --git a/bindings/java/src/main/java/unicorn/RiscvConst.java b/bindings/java/src/main/java/unicorn/RiscvConst.java
@@ -7,15 +7,17 @@ public interface RiscvConst {
     // RISCV32 CPU
 
     public static final int UC_CPU_RISCV32_ANY = 0;
-    public static final int UC_CPU_RISCV32_BASE32 = 1;
-    public static final int UC_CPU_RISCV32_SIFIVE_E31 = 2;
-    public static final int UC_CPU_RISCV32_SIFIVE_U34 = 3;
-    public static final int UC_CPU_RISCV32_ENDING = 4;
+    public static final int UC_CPU_RISCV32_BASE = 1;
+    public static final int UC_CPU_RISCV32_IBEX = 2;
+    public static final int UC_CPU_RISCV32_SIFIVE_E31 = 3;
+    public static final int UC_CPU_RISCV32_SIFIVE_E34 = 4;
+    public static final int UC_CPU_RISCV32_SIFIVE_U34 = 5;
+    public static final int UC_CPU_RISCV32_ENDING = 6;
 
     // RISCV64 CPU
 
     public static final int UC_CPU_RISCV64_ANY = 0;
-    public static final int UC_CPU_RISCV64_BASE64 = 1;
+    public static final int UC_CPU_RISCV64_BASE = 1;
     public static final int UC_CPU_RISCV64_SIFIVE_E51 = 2;
     public static final int UC_CPU_RISCV64_SIFIVE_U54 = 3;
     public static final int UC_CPU_RISCV64_ENDING = 4;
diff --git a/bindings/pascal/unicorn/MipsConst.pas b/bindings/pascal/unicorn/MipsConst.pas
@@ -39,8 +39,10 @@ interface
   UC_CPU_MIPS64_I6500 = 9;
   UC_CPU_MIPS64_LOONGSON_2E = 10;
   UC_CPU_MIPS64_LOONGSON_2F = 11;
-  UC_CPU_MIPS64_MIPS64DSPR2 = 12;
-  UC_CPU_MIPS64_ENDING = 13;
+  UC_CPU_MIPS64_LOONGSON_3A1000 = 12;
+  UC_CPU_MIPS64_LOONGSON_3A4000 = 13;
+  UC_CPU_MIPS64_MIPS64DSPR2 = 14;
+  UC_CPU_MIPS64_ENDING = 15;
 
 // MIPS registers
 
@@ -242,4 +244,4 @@ interface
   UC_MIPS_REG_LO3 = 48;
 
 implementation
-end.
+end.
diff --git a/bindings/pascal/unicorn/RiscvConst.pas b/bindings/pascal/unicorn/RiscvConst.pas
@@ -8,15 +8,17 @@ interface
 // RISCV32 CPU
 
   UC_CPU_RISCV32_ANY = 0;
-  UC_CPU_RISCV32_BASE32 = 1;
-  UC_CPU_RISCV32_SIFIVE_E31 = 2;
-  UC_CPU_RISCV32_SIFIVE_U34 = 3;
-  UC_CPU_RISCV32_ENDING = 4;
+  UC_CPU_RISCV32_BASE = 1;
+  UC_CPU_RISCV32_IBEX = 2;
+  UC_CPU_RISCV32_SIFIVE_E31 = 3;
+  UC_CPU_RISCV32_SIFIVE_E34 = 4;
+  UC_CPU_RISCV32_SIFIVE_U34 = 5;
+  UC_CPU_RISCV32_ENDING = 6;
 
 // RISCV64 CPU
 
   UC_CPU_RISCV64_ANY = 0;
-  UC_CPU_RISCV64_BASE64 = 1;
+  UC_CPU_RISCV64_BASE = 1;
   UC_CPU_RISCV64_SIFIVE_E51 = 2;
   UC_CPU_RISCV64_SIFIVE_U54 = 3;
   UC_CPU_RISCV64_ENDING = 4;
@@ -291,4 +293,4 @@ interface
   UC_RISCV_REG_FT11 = 189;
 
 implementation
-end.
+end.
diff --git a/bindings/python/unicorn/mips_const.py b/bindings/python/unicorn/mips_const.py
@@ -34,8 +34,10 @@
 UC_CPU_MIPS64_I6500 = 9
 UC_CPU_MIPS64_LOONGSON_2E = 10
 UC_CPU_MIPS64_LOONGSON_2F = 11
-UC_CPU_MIPS64_MIPS64DSPR2 = 12
-UC_CPU_MIPS64_ENDING = 13
+UC_CPU_MIPS64_LOONGSON_3A1000 = 12
+UC_CPU_MIPS64_LOONGSON_3A4000 = 13
+UC_CPU_MIPS64_MIPS64DSPR2 = 14
+UC_CPU_MIPS64_ENDING = 15
 
 # MIPS registers
 
diff --git a/bindings/python/unicorn/riscv_const.py b/bindings/python/unicorn/riscv_const.py
@@ -3,15 +3,17 @@
 # RISCV32 CPU
 
 UC_CPU_RISCV32_ANY = 0
-UC_CPU_RISCV32_BASE32 = 1
-UC_CPU_RISCV32_SIFIVE_E31 = 2
-UC_CPU_RISCV32_SIFIVE_U34 = 3
-UC_CPU_RISCV32_ENDING = 4
+UC_CPU_RISCV32_BASE = 1
+UC_CPU_RISCV32_IBEX = 2
+UC_CPU_RISCV32_SIFIVE_E31 = 3
+UC_CPU_RISCV32_SIFIVE_E34 = 4
+UC_CPU_RISCV32_SIFIVE_U34 = 5
+UC_CPU_RISCV32_ENDING = 6
 
 # RISCV64 CPU
 
 UC_CPU_RISCV64_ANY = 0
-UC_CPU_RISCV64_BASE64 = 1
+UC_CPU_RISCV64_BASE = 1
 UC_CPU_RISCV64_SIFIVE_E51 = 2
 UC_CPU_RISCV64_SIFIVE_U54 = 3
 UC_CPU_RISCV64_ENDING = 4
diff --git a/bindings/ruby/unicorn_gem/lib/unicorn_engine/mips_const.rb b/bindings/ruby/unicorn_gem/lib/unicorn_engine/mips_const.rb
@@ -36,8 +36,10 @@ module UnicornEngine
 	UC_CPU_MIPS64_I6500 = 9
 	UC_CPU_MIPS64_LOONGSON_2E = 10
 	UC_CPU_MIPS64_LOONGSON_2F = 11
-	UC_CPU_MIPS64_MIPS64DSPR2 = 12
-	UC_CPU_MIPS64_ENDING = 13
+	UC_CPU_MIPS64_LOONGSON_3A1000 = 12
+	UC_CPU_MIPS64_LOONGSON_3A4000 = 13
+	UC_CPU_MIPS64_MIPS64DSPR2 = 14
+	UC_CPU_MIPS64_ENDING = 15
 
 # MIPS registers
 
diff --git a/bindings/ruby/unicorn_gem/lib/unicorn_engine/riscv_const.rb b/bindings/ruby/unicorn_gem/lib/unicorn_engine/riscv_const.rb
@@ -5,15 +5,17 @@ module UnicornEngine
 # RISCV32 CPU
 
 	UC_CPU_RISCV32_ANY = 0
-	UC_CPU_RISCV32_BASE32 = 1
-	UC_CPU_RISCV32_SIFIVE_E31 = 2
-	UC_CPU_RISCV32_SIFIVE_U34 = 3
-	UC_CPU_RISCV32_ENDING = 4
+	UC_CPU_RISCV32_BASE = 1
+	UC_CPU_RISCV32_IBEX = 2
+	UC_CPU_RISCV32_SIFIVE_E31 = 3
+	UC_CPU_RISCV32_SIFIVE_E34 = 4
+	UC_CPU_RISCV32_SIFIVE_U34 = 5
+	UC_CPU_RISCV32_ENDING = 6
 
 # RISCV64 CPU
 
 	UC_CPU_RISCV64_ANY = 0
-	UC_CPU_RISCV64_BASE64 = 1
+	UC_CPU_RISCV64_BASE = 1
 	UC_CPU_RISCV64_SIFIVE_E51 = 2
 	UC_CPU_RISCV64_SIFIVE_U54 = 3
 	UC_CPU_RISCV64_ENDING = 4
diff --git a/bindings/rust/src/riscv.rs b/bindings/rust/src/riscv.rs
@@ -349,8 +349,10 @@ impl From<RegisterRISCV> for i32 {
 #[derive(Debug, Copy, Clone, PartialEq, Eq)]
 pub enum Riscv32CpuModel {
     UC_CPU_RISCV32_ANY = 0,
-    UC_CPU_RISCV32_BASE32,
+    UC_CPU_RISCV32_BASE,
+    UC_CPU_RISCV32_IBEX,
     UC_CPU_RISCV32_SIFIVE_E31,
+    UC_CPU_RISCV32_SIFIVE_E34,
     UC_CPU_RISCV32_SIFIVE_U34,
 }
 
@@ -370,7 +372,7 @@ impl From<&Riscv32CpuModel> for i32 {
 #[derive(Debug, Copy, Clone, PartialEq, Eq)]
 pub enum Riscv64CpuModel {
     UC_CPU_RISCV64_ANY = 0,
-    UC_CPU_RISCV64_BASE64,
+    UC_CPU_RISCV64_BASE,
     UC_CPU_RISCV64_SIFIVE_E51,
     UC_CPU_RISCV64_SIFIVE_U54,
 }
diff --git a/bindings/zig/unicorn/mips_const.zig b/bindings/zig/unicorn/mips_const.zig
@@ -36,8 +36,10 @@ pub const mipsConst = enum(c_int) {
 	CPU_MIPS64_I6500 = 9,
 	CPU_MIPS64_LOONGSON_2E = 10,
 	CPU_MIPS64_LOONGSON_2F = 11,
-	CPU_MIPS64_MIPS64DSPR2 = 12,
-	CPU_MIPS64_ENDING = 13,
+	CPU_MIPS64_LOONGSON_3A1000 = 12,
+	CPU_MIPS64_LOONGSON_3A4000 = 13,
+	CPU_MIPS64_MIPS64DSPR2 = 14,
+	CPU_MIPS64_ENDING = 15,
 
 // MIPS registers
 
diff --git a/bindings/zig/unicorn/riscv_const.zig b/bindings/zig/unicorn/riscv_const.zig
@@ -5,10 +5,12 @@ pub const riscvConst = enum(c_int) {
 // RISCV32 CPU
 
 	CPU_RISCV32_ANY = 0,
-	CPU_RISCV32_BASE32 = 1,
-	CPU_RISCV32_SIFIVE_E31 = 2,
-	CPU_RISCV32_SIFIVE_U34 = 3,
-	CPU_RISCV32_ENDING = 4,
+	CPU_RISCV32_BASE = 1,
+	CPU_RISCV32_IBEX = 2,
+	CPU_RISCV32_SIFIVE_E31 = 3,
+	CPU_RISCV32_SIFIVE_E34 = 4,
+	CPU_RISCV32_SIFIVE_U34 = 5,
+	CPU_RISCV32_ENDING = 6,
 
 // RISCV64 CPU
 
