qemu/target/avr: add initial Unicorn integration.

Signed-off-by: Glenn Baker <[email protected]>

Author: glennsec

qemu/include/tcg/tcg.h

@@ -712,7 +712,7 @@ struct TCGContext {
     void *tb_ret_addr;
 
     /* target/riscv/translate.c */
-    TCGv cpu_gpr[32], cpu_pc; // also target/mips/translate.c
+    TCGv cpu_gpr[32], cpu_pc; // also target/mips/translate.c, target/avr/translate.c
     TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
     TCGv load_res;
     TCGv load_val;
@@ -807,6 +807,23 @@ struct TCGContext {
 
     char s390x_cpu_reg_names[16][4]; // renamed from original cpu_reg_names[][] to avoid name clash with m68k
     TCGv_i64 regs[16];
+
+    // target/avr/translate.c
+    TCGv cpu_Cf;
+    TCGv cpu_Zf;
+    TCGv cpu_Nf;
+    TCGv cpu_Vf;
+    TCGv cpu_Sf;
+    TCGv cpu_Hf;
+    TCGv cpu_Tf;
+    TCGv cpu_If;
+    TCGv cpu_rampD;
+    TCGv cpu_rampX;
+    TCGv cpu_rampY;
+    TCGv cpu_rampZ;
+    TCGv cpu_eind;
+    TCGv cpu_sp;
+    TCGv cpu_skip;
 };
 
 static inline size_t temp_idx(TCGContext *tcg_ctx, TCGTemp *ts)

qemu/target/avr/cpu-qom.h

@@ -22,12 +22,19 @@
 #define QEMU_AVR_QOM_H
 
 #include "hw/core/cpu.h"
-#include "qom/object.h"
+
+typedef void Object;
+typedef void ObjectClass;
+
+typedef void DeviceState;
+typedef void (*DeviceRealize)(DeviceState *ds);
+typedef void (*DeviceReset)(DeviceState *ds);
 
 #define TYPE_AVR_CPU "avr-cpu"
 
-OBJECT_DECLARE_TYPE(AVRCPU, AVRCPUClass,
-                    AVR_CPU)
+#define AVR_CPU(obj) ((AVRCPU *)obj)
+#define AVR_CPU_CLASS(klass) ((AVRCPUClass *)klass)
+#define AVR_CPU_GET_CLASS(obj) (&((AVRCPU *)obj)->cc)
 
 /**
  *  AVRCPUClass:
@@ -37,13 +44,13 @@ OBJECT_DECLARE_TYPE(AVRCPU, AVRCPUClass,
  *
  *  A AVR CPU model.
  */
-struct AVRCPUClass {
+typedef struct AVRCPUClass {
     /*< private >*/
     CPUClass parent_class;
     /*< public >*/
     DeviceRealize parent_realize;
     DeviceReset parent_reset;
-};
+} AVRCPUClass;
 
 
 #endif /* !defined (QEMU_AVR_CPU_QOM_H) */

qemu/target/avr/cpu.c

@@ -19,11 +19,10 @@
  */
 
 #include "qemu/osdep.h"
-#include "qapi/error.h"
-#include "qemu/qemu-print.h"
 #include "exec/exec-all.h"
 #include "cpu.h"
 #include "disas/dis-asm.h"
+#include "unicorn_helper.h"
 
 static void avr_cpu_set_pc(CPUState *cs, vaddr value)
 {
@@ -56,7 +55,8 @@ static void avr_cpu_reset(DeviceState *ds)
     AVRCPUClass *mcc = AVR_CPU_GET_CLASS(cpu);
     CPUAVRState *env = &cpu->env;
 
-    mcc->parent_reset(ds);
+    if (mcc->parent_reset)
+        mcc->parent_reset(ds);
 
     env->pc_w = 0;
     env->sregI = 1;
@@ -80,29 +80,28 @@ static void avr_cpu_reset(DeviceState *ds)
     memset(env->r, 0, sizeof(env->r));
 }
 
+#if 0
 static void avr_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
 {
     info->mach = bfd_arch_avr;
     info->print_insn = avr_print_insn;
 }
+#endif
 
-static void avr_cpu_realizefn(DeviceState *dev, Error **errp)
+static void avr_cpu_realizefn(DeviceState *dev)
 {
     CPUState *cs = CPU(dev);
     AVRCPUClass *mcc = AVR_CPU_GET_CLASS(dev);
-    Error *local_err = NULL;
 
-    cpu_exec_realizefn(cs, &local_err);
-    if (local_err != NULL) {
-        error_propagate(errp, local_err);
-        return;
-    }
+    cpu_exec_realizefn(cs);
     qemu_init_vcpu(cs);
     cpu_reset(cs);
 
-    mcc->parent_realize(dev, errp);
+    if (mcc->parent_realize)
+        mcc->parent_realize(dev);
 }
 
+#if 0
 static void avr_cpu_set_int(void *opaque, int irq, int level)
 {
     AVRCPU *cpu = opaque;
@@ -120,18 +119,24 @@ static void avr_cpu_set_int(void *opaque, int irq, int level)
         }
     }
 }
+#endif
 
-static void avr_cpu_initfn(Object *obj)
+static void avr_cpu_initfn(Object *obj, struct uc_struct *uc)
 {
     AVRCPU *cpu = AVR_CPU(obj);
+    CPUAVRState *const env = &cpu->env;
 
+    env->uc = uc;
     cpu_set_cpustate_pointers(cpu);
 
+#if 0
     /* Set the number of interrupts supported by the CPU. */
     qdev_init_gpio_in(DEVICE(cpu), avr_cpu_set_int,
                       sizeof(cpu->env.intsrc) * 8);
+#endif
 }
 
+#if 0
 static ObjectClass *avr_cpu_class_by_name(const char *cpu_model)
 {
     ObjectClass *oc;
@@ -143,7 +148,9 @@ static ObjectClass *avr_cpu_class_by_name(const char *cpu_model)
     }
     return oc;
 }
+#endif
 
+#if 0
 static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 {
     AVRCPU *cpu = AVR_CPU(cs);
@@ -182,36 +189,45 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
     }
     qemu_fprintf(f, "\n");
 }
+#endif
 
 static void avr_cpu_class_init(ObjectClass *oc, void *data)
 {
-    DeviceClass *dc = DEVICE_CLASS(oc);
     CPUClass *cc = CPU_CLASS(oc);
     AVRCPUClass *mcc = AVR_CPU_CLASS(oc);
 
-    mcc->parent_realize = dc->realize;
-    dc->realize = avr_cpu_realizefn;
-
-    device_class_set_parent_reset(dc, avr_cpu_reset, &mcc->parent_reset);
+    mcc->parent_realize = NULL;
+    mcc->parent_reset = NULL;
 
+#if 0
     cc->class_by_name = avr_cpu_class_by_name;
+#endif
 
+    cc->reset = avr_cpu_reset;
     cc->has_work = avr_cpu_has_work;
     cc->do_interrupt = avr_cpu_do_interrupt;
     cc->cpu_exec_interrupt = avr_cpu_exec_interrupt;
+#if 0
     cc->dump_state = avr_cpu_dump_state;
+#endif
     cc->set_pc = avr_cpu_set_pc;
+#if 0
     cc->memory_rw_debug = avr_cpu_memory_rw_debug;
+#endif
     cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
     cc->tlb_fill = avr_cpu_tlb_fill;
+#if 0
     cc->vmsd = &vms_avr_cpu;
     cc->disas_set_info = avr_cpu_disas_set_info;
+#endif
     cc->tcg_initialize = avr_cpu_tcg_init;
     cc->synchronize_from_tb = avr_cpu_synchronize_from_tb;
+#if 0
     cc->gdb_read_register = avr_cpu_gdb_read_register;
     cc->gdb_write_register = avr_cpu_gdb_write_register;
     cc->gdb_num_core_regs = 35;
     cc->gdb_core_xml_file = "avr-cpu.xml";
+#endif
 }
 
 /*
@@ -321,11 +337,28 @@ static void avr_avr6_initfn(Object *obj)
 }
 
 typedef struct AVRCPUInfo {
+    int model;
     const char *name;
     void (*initfn)(Object *obj);
 } AVRCPUInfo;
 
+static const AVRCPUInfo avr_cpu_info[] ={
+    {UC_CPU_AVR_AVR5, "avr5", avr_avr5_initfn},
+    {UC_CPU_AVR_AVR51, "avr51", avr_avr51_initfn},
+    {UC_CPU_AVR_AVR6, "avr6", avr_avr6_initfn},
+};
+
+static const AVRCPUInfo *avr_cpu_info_get(int cpu_model)
+{
+    for (int i = 0; i < ARRAY_SIZE(avr_cpu_info); i++) {
+        const AVRCPUInfo *const cip = &avr_cpu_info[i];
+        if (cpu_model == cip->model)
+            return cip;
+    }
+    return NULL;
+}
 
+#if 0
 static void avr_cpu_list_entry(gpointer data, gpointer user_data)
 {
     const char *typename = object_class_get_name(OBJECT_CLASS(data));
@@ -364,3 +397,48 @@ static const TypeInfo avr_cpu_type_info[] = {
 };
 
 DEFINE_TYPES(avr_cpu_type_info)
+#endif
+
+AVRCPU *cpu_avr_init(struct uc_struct *uc)
+{
+    AVRCPU *cpu;
+    CPUState *cs;
+    CPUClass *cc;
+    ObjectClass *oc;
+
+    cpu = calloc(1, sizeof(*cpu));
+    if (cpu == NULL) {
+        return NULL;
+    }
+
+    if (uc->cpu_model == INT_MAX)
+        uc->cpu_model = UC_CPU_AVR_AVR6;
+    const AVRCPUInfo *const cip = avr_cpu_info_get(uc->cpu_model);
+    if (!cip) {
+        free(cpu);
+        return NULL;
+    }
+
+    cs = &cpu->parent_obj;
+    cc = &AVR_CPU_GET_CLASS(cpu)->parent_class;
+    oc = (ObjectClass *)cc;
+    cs->cc = cc;
+    cs->uc = uc;
+    uc->cpu = cs;
+
+    cpu_class_init(uc, cc);
+    avr_cpu_class_init(oc, NULL);
+
+    cpu_common_initfn(uc, cs);
+    avr_cpu_initfn(cs, uc);
+    cip->initfn(cs);
+
+    avr_cpu_realizefn(cs);
+
+    // init address space
+    cpu_address_space_init(cs, 0, cs->memory);
+
+    qemu_init_vcpu(cs);
+
+    return cpu;
+}

qemu/target/avr/cpu.h

@@ -23,6 +23,7 @@
 
 #include "cpu-qom.h"
 #include "exec/cpu-defs.h"
+#include "disas/dis-asm.h"
 
 #ifdef CONFIG_USER_ONLY
 #error "AVR 8-bit does not support user mode"
@@ -137,6 +138,9 @@ struct CPUAVRState {
     bool fullacc; /* CPU/MEM if true MEM only otherwise */
 
     uint64_t features;
+
+    // Unicorn engine
+    struct uc_struct *uc;
 };
 
 /**
@@ -152,6 +156,8 @@ typedef struct AVRCPU {
 
     CPUNegativeOffsetState neg;
     CPUAVRState env;
+
+    AVRCPUClass cc;
 } AVRCPU;
 
 extern const struct VMStateDescription vms_avr_cpu;
@@ -182,7 +188,7 @@ static inline int avr_cpu_mmu_index(CPUAVRState *env, bool ifetch)
     return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX;
 }
 
-void avr_cpu_tcg_init(void);
+void avr_cpu_tcg_init(struct uc_struct *uc);
 
 void avr_cpu_list(void);
 int cpu_avr_exec(CPUState *cpu);