Skip to content

Commit b6306df

Browse files
amaanqamaanq
committed
feat!: update MIPS to 5.1.0
1 parent deac5a8 commit b6306df

File tree

11 files changed

+1516
-383
lines changed

11 files changed

+1516
-383
lines changed

‎qemu/target/mips/cp0_helper.c‎

Lines changed: 3 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -378,16 +378,9 @@ target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
378378
target_ulong helper_mftc0_cause(CPUMIPSState *env)
379379
{
380380
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
381-
int32_t tccause;
382381
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
383382

384-
if (other_tc == other->current_tc) {
385-
tccause = other->CP0_Cause;
386-
} else {
387-
tccause = other->CP0_Cause;
388-
}
389-
390-
return tccause;
383+
return other->CP0_Cause;
391384
}
392385

393386
target_ulong helper_mftc0_status(CPUMIPSState *env)
@@ -877,6 +870,7 @@ void helper_mtc0_memorymapid(CPUMIPSState *env, target_ulong arg1)
877870

878871
void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask)
879872
{
873+
struct uc_struct *uc = env->uc;
880874
uint64_t mask = arg1 >> (TARGET_PAGE_BITS + 1);
881875
if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 == ~0) ||
882876
(mask == 0x0000 || mask == 0x0003 || mask == 0x000F ||
@@ -1113,6 +1107,7 @@ void helper_mthc0_saar(CPUMIPSState *env, target_ulong arg1)
11131107

11141108
void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
11151109
{
1110+
struct uc_struct *uc = env->uc;
11161111
target_ulong old, val, mask;
11171112
mask = (TARGET_PAGE_MASK << 1) | env->CP0_EntryHi_ASID_mask;
11181113
if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) {

‎qemu/target/mips/cpu-param.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,8 @@
1919
#define TARGET_PHYS_ADDR_SPACE_BITS 40
2020
#define TARGET_VIRT_ADDR_SPACE_BITS 32
2121
#endif
22-
#define TARGET_PAGE_BITS 12
22+
#define TARGET_PAGE_BITS_VARY
23+
#define TARGET_PAGE_BITS_MIN 12
2324
#define NB_MMU_MODES 4
2425

2526
#endif

‎qemu/target/mips/cpu.h‎

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -940,7 +940,35 @@ struct CPUMIPSState {
940940
#define CP0C5_UFR 2
941941
#define CP0C5_NFExists 0
942942
int32_t CP0_Config6;
943+
int32_t CP0_Config6_rw_bitmask;
944+
#define CP0C6_BPPASS 31
945+
#define CP0C6_KPOS 24
946+
#define CP0C6_KE 23
947+
#define CP0C6_VTLBONLY 22
948+
#define CP0C6_LASX 21
949+
#define CP0C6_SSEN 20
950+
#define CP0C6_DISDRTIME 19
951+
#define CP0C6_PIXNUEN 18
952+
#define CP0C6_SCRAND 17
953+
#define CP0C6_LLEXCEN 16
954+
#define CP0C6_DISVC 15
955+
#define CP0C6_VCLRU 14
956+
#define CP0C6_DCLRU 13
957+
#define CP0C6_PIXUEN 12
958+
#define CP0C6_DISBLKLYEN 11
959+
#define CP0C6_UMEMUALEN 10
960+
#define CP0C6_SFBEN 8
961+
#define CP0C6_FLTINT 7
962+
#define CP0C6_VLTINT 6
963+
#define CP0C6_DISBTB 5
964+
#define CP0C6_STPREFCTL 2
965+
#define CP0C6_INSTPREF 1
966+
#define CP0C6_DATAPREF 0
943967
int32_t CP0_Config7;
968+
int64_t CP0_Config7_rw_bitmask;
969+
#define CP0C7_NAPCGEN 2
970+
#define CP0C7_UNIMUEN 1
971+
#define CP0C7_VFPUCGEN 0
944972
uint64_t CP0_LLAddr;
945973
uint64_t CP0_MAAR[MIPS_MAAR_MAX];
946974
int32_t CP0_MAARI;

‎qemu/target/mips/helper.c‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -68,6 +68,7 @@ int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
6868
int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
6969
target_ulong address, int rw, int access_type)
7070
{
71+
struct uc_struct *uc = env->uc;
7172
uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
7273
uint32_t MMID = env->CP0_MemoryMapID;
7374
bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1);
@@ -461,6 +462,7 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
461462
static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
462463
int rw, int tlb_error)
463464
{
465+
struct uc_struct *uc = env->uc;
464466
CPUState *cs = env_cpu(env);
465467
int exception = 0, error_code = 0;
466468

@@ -903,6 +905,7 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
903905
{
904906
MIPSCPU *cpu = MIPS_CPU(cs);
905907
CPUMIPSState *env = &cpu->env;
908+
struct uc_struct *uc = env->uc;
906909
hwaddr physical;
907910
int prot;
908911
int mips_access_type;
@@ -1424,6 +1427,7 @@ bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
14241427

14251428
void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra)
14261429
{
1430+
struct uc_struct *uc = env->uc;
14271431
CPUState *cs = env_cpu(env);
14281432
r4k_tlb_t *tlb;
14291433
target_ulong addr;

‎qemu/target/mips/helper.h‎

Lines changed: 59 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -945,6 +945,21 @@ DEF_HELPER_4(msa_mod_s_h, void, env, i32, i32, i32)
945945
DEF_HELPER_4(msa_mod_s_w, void, env, i32, i32, i32)
946946
DEF_HELPER_4(msa_mod_s_d, void, env, i32, i32, i32)
947947

948+
DEF_HELPER_4(msa_maddv_b, void, env, i32, i32, i32)
949+
DEF_HELPER_4(msa_maddv_h, void, env, i32, i32, i32)
950+
DEF_HELPER_4(msa_maddv_w, void, env, i32, i32, i32)
951+
DEF_HELPER_4(msa_maddv_d, void, env, i32, i32, i32)
952+
953+
DEF_HELPER_4(msa_msubv_b, void, env, i32, i32, i32)
954+
DEF_HELPER_4(msa_msubv_h, void, env, i32, i32, i32)
955+
DEF_HELPER_4(msa_msubv_w, void, env, i32, i32, i32)
956+
DEF_HELPER_4(msa_msubv_d, void, env, i32, i32, i32)
957+
958+
DEF_HELPER_4(msa_mulv_b, void, env, i32, i32, i32)
959+
DEF_HELPER_4(msa_mulv_h, void, env, i32, i32, i32)
960+
DEF_HELPER_4(msa_mulv_w, void, env, i32, i32, i32)
961+
DEF_HELPER_4(msa_mulv_d, void, env, i32, i32, i32)
962+
948963
DEF_HELPER_4(msa_asub_s_b, void, env, i32, i32, i32)
949964
DEF_HELPER_4(msa_asub_s_h, void, env, i32, i32, i32)
950965
DEF_HELPER_4(msa_asub_s_w, void, env, i32, i32, i32)
@@ -963,6 +978,31 @@ DEF_HELPER_4(msa_hsub_u_h, void, env, i32, i32, i32)
963978
DEF_HELPER_4(msa_hsub_u_w, void, env, i32, i32, i32)
964979
DEF_HELPER_4(msa_hsub_u_d, void, env, i32, i32, i32)
965980

981+
DEF_HELPER_4(msa_subs_s_b, void, env, i32, i32, i32)
982+
DEF_HELPER_4(msa_subs_s_h, void, env, i32, i32, i32)
983+
DEF_HELPER_4(msa_subs_s_w, void, env, i32, i32, i32)
984+
DEF_HELPER_4(msa_subs_s_d, void, env, i32, i32, i32)
985+
986+
DEF_HELPER_4(msa_subs_u_b, void, env, i32, i32, i32)
987+
DEF_HELPER_4(msa_subs_u_h, void, env, i32, i32, i32)
988+
DEF_HELPER_4(msa_subs_u_w, void, env, i32, i32, i32)
989+
DEF_HELPER_4(msa_subs_u_d, void, env, i32, i32, i32)
990+
991+
DEF_HELPER_4(msa_subsus_u_b, void, env, i32, i32, i32)
992+
DEF_HELPER_4(msa_subsus_u_h, void, env, i32, i32, i32)
993+
DEF_HELPER_4(msa_subsus_u_w, void, env, i32, i32, i32)
994+
DEF_HELPER_4(msa_subsus_u_d, void, env, i32, i32, i32)
995+
996+
DEF_HELPER_4(msa_subsuu_s_b, void, env, i32, i32, i32)
997+
DEF_HELPER_4(msa_subsuu_s_h, void, env, i32, i32, i32)
998+
DEF_HELPER_4(msa_subsuu_s_w, void, env, i32, i32, i32)
999+
DEF_HELPER_4(msa_subsuu_s_d, void, env, i32, i32, i32)
1000+
1001+
DEF_HELPER_4(msa_subv_b, void, env, i32, i32, i32)
1002+
DEF_HELPER_4(msa_subv_h, void, env, i32, i32, i32)
1003+
DEF_HELPER_4(msa_subv_w, void, env, i32, i32, i32)
1004+
DEF_HELPER_4(msa_subv_d, void, env, i32, i32, i32)
1005+
9661006
DEF_HELPER_4(msa_ilvev_b, void, env, i32, i32, i32)
9671007
DEF_HELPER_4(msa_ilvev_h, void, env, i32, i32, i32)
9681008
DEF_HELPER_4(msa_ilvev_w, void, env, i32, i32, i32)
@@ -1058,20 +1098,25 @@ DEF_HELPER_5(msa_srlri_df, void, env, i32, i32, i32, i32)
10581098

10591099
DEF_HELPER_5(msa_binsl_df, void, env, i32, i32, i32, i32)
10601100
DEF_HELPER_5(msa_binsr_df, void, env, i32, i32, i32, i32)
1061-
DEF_HELPER_5(msa_subv_df, void, env, i32, i32, i32, i32)
1062-
DEF_HELPER_5(msa_subs_s_df, void, env, i32, i32, i32, i32)
1063-
DEF_HELPER_5(msa_subs_u_df, void, env, i32, i32, i32, i32)
1064-
DEF_HELPER_5(msa_subsus_u_df, void, env, i32, i32, i32, i32)
1065-
DEF_HELPER_5(msa_subsuu_s_df, void, env, i32, i32, i32, i32)
1066-
DEF_HELPER_5(msa_mulv_df, void, env, i32, i32, i32, i32)
1067-
DEF_HELPER_5(msa_maddv_df, void, env, i32, i32, i32, i32)
1068-
DEF_HELPER_5(msa_msubv_df, void, env, i32, i32, i32, i32)
1069-
DEF_HELPER_5(msa_dotp_s_df, void, env, i32, i32, i32, i32)
1070-
DEF_HELPER_5(msa_dotp_u_df, void, env, i32, i32, i32, i32)
1071-
DEF_HELPER_5(msa_dpadd_s_df, void, env, i32, i32, i32, i32)
1072-
DEF_HELPER_5(msa_dpadd_u_df, void, env, i32, i32, i32, i32)
1073-
DEF_HELPER_5(msa_dpsub_s_df, void, env, i32, i32, i32, i32)
1074-
DEF_HELPER_5(msa_dpsub_u_df, void, env, i32, i32, i32, i32)
1101+
1102+
DEF_HELPER_4(msa_dotp_s_h, void, env, i32, i32, i32)
1103+
DEF_HELPER_4(msa_dotp_s_w, void, env, i32, i32, i32)
1104+
DEF_HELPER_4(msa_dotp_s_d, void, env, i32, i32, i32)
1105+
DEF_HELPER_4(msa_dotp_u_h, void, env, i32, i32, i32)
1106+
DEF_HELPER_4(msa_dotp_u_w, void, env, i32, i32, i32)
1107+
DEF_HELPER_4(msa_dotp_u_d, void, env, i32, i32, i32)
1108+
DEF_HELPER_4(msa_dpadd_s_h, void, env, i32, i32, i32)
1109+
DEF_HELPER_4(msa_dpadd_s_w, void, env, i32, i32, i32)
1110+
DEF_HELPER_4(msa_dpadd_s_d, void, env, i32, i32, i32)
1111+
DEF_HELPER_4(msa_dpadd_u_h, void, env, i32, i32, i32)
1112+
DEF_HELPER_4(msa_dpadd_u_w, void, env, i32, i32, i32)
1113+
DEF_HELPER_4(msa_dpadd_u_d, void, env, i32, i32, i32)
1114+
DEF_HELPER_4(msa_dpsub_s_h, void, env, i32, i32, i32)
1115+
DEF_HELPER_4(msa_dpsub_s_w, void, env, i32, i32, i32)
1116+
DEF_HELPER_4(msa_dpsub_s_d, void, env, i32, i32, i32)
1117+
DEF_HELPER_4(msa_dpsub_u_h, void, env, i32, i32, i32)
1118+
DEF_HELPER_4(msa_dpsub_u_w, void, env, i32, i32, i32)
1119+
DEF_HELPER_4(msa_dpsub_u_d, void, env, i32, i32, i32)
10751120
DEF_HELPER_5(msa_sld_df, void, env, i32, i32, i32, i32)
10761121
DEF_HELPER_5(msa_splat_df, void, env, i32, i32, i32, i32)
10771122
DEF_HELPER_5(msa_vshf_df, void, env, i32, i32, i32, i32)

‎qemu/target/mips/internal.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,9 @@ struct mips_def_t {
3939
int32_t CP0_Config5;
4040
int32_t CP0_Config5_rw_bitmask;
4141
int32_t CP0_Config6;
42+
int32_t CP0_Config6_rw_bitmask;
4243
int32_t CP0_Config7;
44+
int32_t CP0_Config7_rw_bitmask;
4345
target_ulong CP0_LLAddr_rw_bitmask;
4446
int CP0_LLAddr_shift;
4547
int32_t SYNCI_Step;
@@ -217,7 +219,6 @@ uint32_t float_class_s(uint32_t arg, float_status *fst);
217219
uint64_t float_class_d(uint64_t arg, float_status *fst);
218220

219221
extern unsigned int ieee_rm[];
220-
int ieee_ex_to_mips(int xcpt);
221222
void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
222223

223224
static inline void restore_rounding_mode(CPUMIPSState *env)

‎qemu/target/mips/mips-defs.h‎

Lines changed: 30 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@
1515
* ------------------------------------------------
1616
*/
1717
/*
18-
* bits 0-31: MIPS base instruction sets
18+
* bits 0-23: MIPS base instruction sets
1919
*/
2020
#define ISA_MIPS1 0x0000000000000001ULL
2121
#define ISA_MIPS2 0x0000000000000002ULL
@@ -34,30 +34,37 @@
3434
#define ISA_MIPS64R6 0x0000000000004000ULL
3535
#define ISA_NANOMIPS32 0x0000000000008000ULL
3636
/*
37-
* bits 32-47: MIPS ASEs
37+
* bits 24-39: MIPS ASEs
3838
*/
39-
#define ASE_MIPS16 0x0000000100000000ULL
40-
#define ASE_MIPS3D 0x0000000200000000ULL
41-
#define ASE_MDMX 0x0000000400000000ULL
42-
#define ASE_DSP 0x0000000800000000ULL
43-
#define ASE_DSP_R2 0x0000001000000000ULL
44-
#define ASE_DSP_R3 0x0000002000000000ULL
45-
#define ASE_MT 0x0000004000000000ULL
46-
#define ASE_SMARTMIPS 0x0000008000000000ULL
47-
#define ASE_MICROMIPS 0x0000010000000000ULL
48-
#define ASE_MSA 0x0000020000000000ULL
39+
#define ASE_MIPS16 0x0000000001000000ULL
40+
#define ASE_MIPS3D 0x0000000002000000ULL
41+
#define ASE_MDMX 0x0000000004000000ULL
42+
#define ASE_DSP 0x0000000008000000ULL
43+
#define ASE_DSP_R2 0x0000000010000000ULL
44+
#define ASE_DSP_R3 0x0000000020000000ULL
45+
#define ASE_MT 0x0000000040000000ULL
46+
#define ASE_SMARTMIPS 0x0000000080000000ULL
47+
#define ASE_MICROMIPS 0x0000000100000000ULL
48+
#define ASE_MSA 0x0000000200000000ULL
4949
/*
50-
* bits 48-55: vendor-specific base instruction sets
50+
* bits 40-51: vendor-specific base instruction sets
5151
*/
52-
#define INSN_LOONGSON2E 0x0001000000000000ULL
53-
#define INSN_LOONGSON2F 0x0002000000000000ULL
54-
#define INSN_VR54XX 0x0004000000000000ULL
55-
#define INSN_R5900 0x0008000000000000ULL
52+
#define INSN_VR54XX 0x0000010000000000ULL
53+
#define INSN_R5900 0x0000020000000000ULL
54+
#define INSN_LOONGSON2E 0x0000040000000000ULL
55+
#define INSN_LOONGSON2F 0x0000080000000000ULL
56+
#define INSN_LOONGSON3A 0x0000100000000000ULL
5657
/*
57-
* bits 56-63: vendor-specific ASEs
58+
* bits 52-63: vendor-specific ASEs
5859
*/
59-
#define ASE_MMI 0x0100000000000000ULL
60-
#define ASE_MXU 0x0200000000000000ULL
60+
/* MultiMedia Instructions defined by R5900 */
61+
#define ASE_MMI 0x0010000000000000ULL
62+
/* MIPS eXtension/enhanced Unit defined by Ingenic */
63+
#define ASE_MXU 0x0020000000000000ULL
64+
/* Loongson MultiMedia Instructions */
65+
#define ASE_LMMI 0x0040000000000000ULL
66+
/* Loongson EXTensions */
67+
#define ASE_LEXT 0x0080000000000000ULL
6168

6269
/* MIPS CPU defines. */
6370
#define CPU_MIPS1 (ISA_MIPS1)
@@ -67,7 +74,7 @@
6774
#define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX)
6875
#define CPU_R5900 (CPU_MIPS3 | INSN_R5900)
6976
#define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E)
70-
#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F)
77+
#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI)
7178

7279
#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5)
7380

@@ -94,6 +101,8 @@
94101
/* Wave Computing: "nanoMIPS" */
95102
#define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32)
96103

104+
#define CPU_LOONGSON3A (CPU_MIPS64R2 | INSN_LOONGSON3A | ASE_LMMI | ASE_LEXT)
105+
97106
/*
98107
* Strictly follow the architecture standard:
99108
* - Disallow "special" instruction handling for PMON/SPIM.

0 commit comments

Comments
 (0)