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AVR: update for new v2.1.x APIs.
Signed-off-by: Glenn Baker <[email protected]>
1 parent fda0d8b commit ea387a2

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4 files changed

+58
-87
lines changed

4 files changed

+58
-87
lines changed

‎qemu/avr.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1288,4 +1288,8 @@
12881288
#define helper_wdr helper_wdr_avr
12891289
#define gen_intermediate_code gen_intermediate_code_avr
12901290
#define restore_state_to_opc restore_state_to_opc_avr
1291+
1292+
#define reg_read reg_read_avr
1293+
#define reg_write reg_write_avr
1294+
#define uc_init uc_init_avr
12911295
#endif

‎qemu/target/avr/unicorn.c

Lines changed: 46 additions & 72 deletions
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@ static void avr_set_pc(struct uc_struct *uc, uint64_t address)
3636
set_pc((CPUAVRState *)uc->cpu->env_ptr, address);
3737
}
3838

39-
void avr_reg_reset(struct uc_struct *uc)
39+
static void reg_reset(struct uc_struct *uc)
4040
{
4141
}
4242

@@ -45,126 +45,130 @@ void avr_reg_reset(struct uc_struct *uc)
4545
#define GET_RAMP(reg) GET_BYTE(env->glue(ramp,reg), 2)
4646
#define SET_RAMP(reg, val) SET_BYTE(env->glue(ramp,reg), 2, val)
4747

48-
static void reg_read(CPUAVRState *env, unsigned int regid, void *value)
48+
DEFAULT_VISIBILITY
49+
uc_err reg_read(void *_env, int mode, unsigned int regid, void *value,
50+
size_t *size)
4951
{
52+
CPUAVRState *const env = _env;
53+
uc_err ret = UC_ERR_ARG;
54+
5055
switch (regid) {
5156
case UC_AVR_REG_PC:
57+
CHECK_REG_TYPE(uint32_t);
5258
*(uint32_t *)value = get_pc(env);
5359
break;
5460
case UC_AVR_REG_SP:
61+
CHECK_REG_TYPE(uint32_t);
5562
*(uint32_t *)value = env->sp;
5663
break;
5764

5865
case UC_AVR_REG_RAMPD:
66+
CHECK_REG_TYPE(uint8_t);
5967
*(uint8_t *)value = GET_RAMP(D);
6068
break;
6169
case UC_AVR_REG_RAMPX:
70+
CHECK_REG_TYPE(uint8_t);
6271
*(uint8_t *)value = GET_RAMP(X);
6372
break;
6473
case UC_AVR_REG_RAMPY:
74+
CHECK_REG_TYPE(uint8_t);
6575
*(uint8_t *)value = GET_RAMP(Y);
6676
break;
6777
case UC_AVR_REG_RAMPZ:
78+
CHECK_REG_TYPE(uint8_t);
6879
*(uint8_t *)value = GET_RAMP(Z);
6980
break;
7081
case UC_AVR_REG_EIND:
82+
CHECK_REG_TYPE(uint8_t);
7183
*(uint8_t *)value = GET_BYTE(env->eind, 2);
7284
break;
7385
case UC_AVR_REG_SPL:
86+
CHECK_REG_TYPE(uint8_t);
7487
*(uint8_t *)value = GET_BYTE(env->sp, 0);
7588
break;
7689
case UC_AVR_REG_SPH:
90+
CHECK_REG_TYPE(uint8_t);
7791
*(uint8_t *)value = GET_BYTE(env->sp, 1);
7892
break;
7993
case UC_AVR_REG_SREG:
94+
CHECK_REG_TYPE(uint8_t);
8095
*(uint8_t *)value = cpu_get_sreg(env);
8196
break;
8297

8398
default: {
8499
uint64_t v = 0;
85100
if (regid >= UC_AVR_REG_R0 && regid <= UC_AVR_REG_R31) {
101+
CHECK_REG_TYPE(uint8_t);
86102
*(int8_t *)value = (int8_t)env->r[regid - UC_AVR_REG_R0];
87103
}
88104
else if (regid >= UC_AVR_REG_R0W && regid <= UC_AVR_REG_R30W) {
89105
const uint32_t *const r = &env->r[regid - UC_AVR_REG_R0W];
90106
for (int k = 0; k < 2; k++)
91107
SET_BYTE(v, k, (r[k] & 0xff));
108+
CHECK_REG_TYPE(uint16_t);
92109
*(int16_t *)value = (int16_t)v;
93110
}
94111
else if (regid >= UC_AVR_REG_R0D && regid <= UC_AVR_REG_R28D) {
95112
const uint32_t *const r = &env->r[regid - UC_AVR_REG_R0D];
96113
for (int k = 0; k < 4; k++)
97114
SET_BYTE(v, k, (r[k] & 0xff));
115+
CHECK_REG_TYPE(uint32_t);
98116
*(int32_t *)value = (int32_t)v;
99117
}
100118
break;
101119
}
102120
}
121+
return ret;
103122
}
104123

105-
int avr_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals,
106-
int count)
124+
DEFAULT_VISIBILITY
125+
uc_err reg_write(void *_env, int mode, unsigned int regid, const void *value,
126+
size_t *size, int *setpc)
107127
{
108-
CPUAVRState *env = &(AVR_CPU(uc->cpu)->env);
109-
int i;
128+
CPUAVRState *const env = _env;
129+
uc_err ret = UC_ERR_ARG;
110130

111-
for (i = 0; i < count; i++) {
112-
unsigned int regid = regs[i];
113-
void *value = vals[i];
114-
reg_read(env, regid, value);
115-
}
116-
117-
return 0;
118-
}
119-
120-
int avr_context_reg_read(struct uc_context *uc, unsigned int *regs,
121-
void **vals, int count)
122-
{
123-
CPUAVRState *env = (CPUAVRState *)uc->data;
124-
int i;
125-
126-
for (i = 0; i < count; i++) {
127-
unsigned int regid = regs[i];
128-
void *value = vals[i];
129-
reg_read(env, regid, value);
130-
}
131-
132-
return 0;
133-
}
134-
135-
static void reg_write(CPUAVRState *env, unsigned int regid,
136-
const void *value)
137-
{
138131
switch (regid) {
139132
case UC_AVR_REG_PC:
133+
CHECK_REG_TYPE(uint32_t);
140134
set_pc(env, *(uint32_t *)value);
135+
*setpc = 1;
141136
break;
142137
case UC_AVR_REG_SP:
138+
CHECK_REG_TYPE(uint32_t);
143139
env->sp = *(uint32_t *)value;
144140
break;
145141

146142
case UC_AVR_REG_RAMPD:
143+
CHECK_REG_TYPE(uint8_t);
147144
SET_RAMP(D, *(uint8_t *)value);
148145
break;
149146
case UC_AVR_REG_RAMPX:
147+
CHECK_REG_TYPE(uint8_t);
150148
SET_RAMP(X, *(uint8_t *)value);
151149
break;
152150
case UC_AVR_REG_RAMPY:
151+
CHECK_REG_TYPE(uint8_t);
153152
SET_RAMP(Y, *(uint8_t *)value);
154153
break;
155154
case UC_AVR_REG_RAMPZ:
155+
CHECK_REG_TYPE(uint8_t);
156156
SET_RAMP(Z, *(uint8_t *)value);
157157
break;
158158
case UC_AVR_REG_EIND:
159+
CHECK_REG_TYPE(uint8_t);
159160
SET_BYTE(env->eind, 2, *(uint8_t *)value);
160161
break;
161162
case UC_AVR_REG_SPL:
163+
CHECK_REG_TYPE(uint8_t);
162164
SET_BYTE(env->sp, 0, *(uint8_t *)value);
163165
break;
164166
case UC_AVR_REG_SPH:
167+
CHECK_REG_TYPE(uint8_t);
165168
SET_BYTE(env->sp, 1, *(uint8_t *)value);
166169
break;
167170
case UC_AVR_REG_SREG:
171+
CHECK_REG_TYPE(uint8_t);
168172
cpu_set_sreg(env, *(uint8_t *)value);
169173
break;
170174

@@ -176,58 +180,27 @@ static void reg_write(CPUAVRState *env, unsigned int regid,
176180
v = *(uint8_t *)value;
177181
r = &env->r[regid - UC_AVR_REG_R0];
178182
rlen = 1;
183+
CHECK_REG_TYPE(uint8_t);
179184
}
180185
else if (regid >= UC_AVR_REG_R0W && regid <= UC_AVR_REG_R30W) {
181186
v = *(uint16_t *)value;
182187
r = &env->r[regid - UC_AVR_REG_R0W];
183188
rlen = 2;
189+
CHECK_REG_TYPE(uint16_t);
184190
}
185191
else if (regid >= UC_AVR_REG_R0D && regid <= UC_AVR_REG_R28D) {
186192
v = *(uint32_t *)value;
187193
r = &env->r[regid - UC_AVR_REG_R0D];
188194
rlen = 4;
195+
CHECK_REG_TYPE(uint32_t);
189196
}
190197
if (r && rlen > 0) {
191198
for (int k = 0; k < rlen; k++)
192199
r[k] = GET_BYTE(v, k);
193200
}
194201
}
195202
}
196-
}
197-
198-
int avr_reg_write(struct uc_struct *uc, unsigned int *regs,
199-
void *const *vals, int count)
200-
{
201-
CPUAVRState *env = &(AVR_CPU(uc->cpu)->env);
202-
int i;
203-
204-
for (i = 0; i < count; i++) {
205-
unsigned int regid = regs[i];
206-
void *value = vals[i];
207-
reg_write(env, regid, value);
208-
if (regid == UC_AVR_REG_PC) {
209-
// force to quit execution and flush TB
210-
uc->quit_request = true;
211-
uc_emu_stop(uc);
212-
}
213-
}
214-
215-
return 0;
216-
}
217-
218-
int avr_context_reg_write(struct uc_context *uc, unsigned int *regs,
219-
void *const *vals, int count)
220-
{
221-
CPUAVRState *env = (CPUAVRState *)uc->data;
222-
int i;
223-
224-
for (i = 0; i < count; i++) {
225-
unsigned int regid = regs[i];
226-
const void *value = vals[i];
227-
reg_write(env, regid, value);
228-
}
229-
230-
return 0;
203+
return ret;
231204
}
232205

233206
static int avr_cpus_init(struct uc_struct *uc, const char *cpu_model)
@@ -286,11 +259,12 @@ static MemoryRegion *avr_memory_map_ptr(struct uc_struct *uc, hwaddr begin, size
286259
return mr;
287260
}
288261

289-
void avr_uc_init(struct uc_struct *uc)
262+
DEFAULT_VISIBILITY
263+
void uc_init(struct uc_struct *uc)
290264
{
291-
uc->reg_read = avr_reg_read;
292-
uc->reg_write = avr_reg_write;
293-
uc->reg_reset = avr_reg_reset;
265+
uc->reg_read = reg_read;
266+
uc->reg_write = reg_write;
267+
uc->reg_reset = reg_reset;
294268
uc->set_pc = avr_set_pc;
295269
uc->get_pc = avr_get_pc;
296270
uc->cpus_init = avr_cpus_init;

‎qemu/target/avr/unicorn.h

Lines changed: 5 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -9,19 +9,12 @@
99
#define UC_QEMU_TARGET_AVR_H
1010

1111
// functions to read & write registers
12-
int avr_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals,
13-
int count);
14-
int avr_reg_write(struct uc_struct *uc, unsigned int *regs,
15-
void *const *vals, int count);
12+
uc_err reg_read_avr(void *env, int mode, unsigned int regid, void *value,
13+
size_t *size);
14+
uc_err reg_write_avr(void *env, int mode, unsigned int regid,
15+
const void *value, size_t *size, int *setpc);
1616

17-
int avr_context_reg_read(struct uc_context *uc, unsigned int *regs,
18-
void **vals, int count);
19-
int avr_context_reg_write(struct uc_context *uc, unsigned int *regs,
20-
void *const *vals, int count);
21-
22-
void avr_reg_reset(struct uc_struct *uc);
23-
24-
void avr_uc_init(struct uc_struct *uc);
17+
void uc_init_avr(struct uc_struct *uc);
2518

2619
int avr_cpu_model_valid(int cpu_model);
2720

‎uc.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -486,7 +486,7 @@ uc_err uc_open(uc_arch arch, uc_mode mode, uc_engine **result)
486486
free(uc);
487487
return UC_ERR_MODE;
488488
}
489-
uc->init_arch = avr_uc_init;
489+
uc->init_arch = uc_init_avr;
490490
break;
491491
#endif
492492
}
@@ -2298,8 +2298,8 @@ static context_reg_rw_t find_context_reg_rw(uc_arch arch, uc_mode mode)
22982298
#endif
22992299
#ifdef UNICORN_HAS_AVR
23002300
case UC_ARCH_AVR:
2301-
rw->context_reg_read = avr_context_reg_read;
2302-
rw->context_reg_write = avr_context_reg_write;
2301+
rw.read = reg_read_avr;
2302+
rw.write = reg_write_avr;
23032303
break;
23042304
#endif
23052305
}

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