diff --git a/bindings/dotnet/UnicornManaged/Const/Arm64.fs b/bindings/dotnet/UnicornManaged/Const/Arm64.fs
index fb13574d11..659a81b389 100644
--- a/bindings/dotnet/UnicornManaged/Const/Arm64.fs
+++ b/bindings/dotnet/UnicornManaged/Const/Arm64.fs
@@ -273,12 +273,13 @@ module Arm64 =
     // pseudo registers
     let UC_ARM64_REG_PC = 260
     let UC_ARM64_REG_CPACR_EL1 = 261
+    let UC_ARM64_REG_ESR = 262
 
     // thread registers
-    let UC_ARM64_REG_TPIDR_EL0 = 262
-    let UC_ARM64_REG_TPIDRRO_EL0 = 263
-    let UC_ARM64_REG_TPIDR_EL1 = 264
-    let UC_ARM64_REG_ENDING = 265
+    let UC_ARM64_REG_TPIDR_EL0 = 263
+    let UC_ARM64_REG_TPIDRRO_EL0 = 264
+    let UC_ARM64_REG_TPIDR_EL1 = 265
+    let UC_ARM64_REG_ENDING = 266
 
     // alias registers
     let UC_ARM64_REG_IP1 = 215
diff --git a/bindings/go/unicorn/arm64_const.go b/bindings/go/unicorn/arm64_const.go
index cfefc1b95b..3b6eaf3589 100644
--- a/bindings/go/unicorn/arm64_const.go
+++ b/bindings/go/unicorn/arm64_const.go
@@ -268,12 +268,13 @@ const (
 // pseudo registers
 	ARM64_REG_PC = 260
 	ARM64_REG_CPACR_EL1 = 261
+	ARM64_REG_ESR = 262
 
 // thread registers
-	ARM64_REG_TPIDR_EL0 = 262
-	ARM64_REG_TPIDRRO_EL0 = 263
-	ARM64_REG_TPIDR_EL1 = 264
-	ARM64_REG_ENDING = 265
+	ARM64_REG_TPIDR_EL0 = 263
+	ARM64_REG_TPIDRRO_EL0 = 264
+	ARM64_REG_TPIDR_EL1 = 265
+	ARM64_REG_ENDING = 266
 
 // alias registers
 	ARM64_REG_IP1 = 215
diff --git a/bindings/java/unicorn/Arm64Const.java b/bindings/java/unicorn/Arm64Const.java
index 7a35434d6c..a094418f38 100644
--- a/bindings/java/unicorn/Arm64Const.java
+++ b/bindings/java/unicorn/Arm64Const.java
@@ -270,12 +270,13 @@ public interface Arm64Const {
 // pseudo registers
    public static final int UC_ARM64_REG_PC = 260;
    public static final int UC_ARM64_REG_CPACR_EL1 = 261;
+   public static final int UC_ARM64_REG_ESR = 262;
 
 // thread registers
-   public static final int UC_ARM64_REG_TPIDR_EL0 = 262;
-   public static final int UC_ARM64_REG_TPIDRRO_EL0 = 263;
-   public static final int UC_ARM64_REG_TPIDR_EL1 = 264;
-   public static final int UC_ARM64_REG_ENDING = 265;
+   public static final int UC_ARM64_REG_TPIDR_EL0 = 263;
+   public static final int UC_ARM64_REG_TPIDRRO_EL0 = 264;
+   public static final int UC_ARM64_REG_TPIDR_EL1 = 265;
+   public static final int UC_ARM64_REG_ENDING = 266;
 
 // alias registers
    public static final int UC_ARM64_REG_IP1 = 215;
diff --git a/bindings/python/unicorn/arm64_const.py b/bindings/python/unicorn/arm64_const.py
index 9b731d026a..4c960d6908 100644
--- a/bindings/python/unicorn/arm64_const.py
+++ b/bindings/python/unicorn/arm64_const.py
@@ -266,12 +266,13 @@
 # pseudo registers
 UC_ARM64_REG_PC = 260
 UC_ARM64_REG_CPACR_EL1 = 261
+UC_ARM64_REG_ESR = 262
 
 # thread registers
-UC_ARM64_REG_TPIDR_EL0 = 262
-UC_ARM64_REG_TPIDRRO_EL0 = 263
-UC_ARM64_REG_TPIDR_EL1 = 264
-UC_ARM64_REG_ENDING = 265
+UC_ARM64_REG_TPIDR_EL0 = 263
+UC_ARM64_REG_TPIDRRO_EL0 = 264
+UC_ARM64_REG_TPIDR_EL1 = 265
+UC_ARM64_REG_ENDING = 266
 
 # alias registers
 UC_ARM64_REG_IP1 = 215
diff --git a/bindings/ruby/unicorn_gem/lib/unicorn/arm64_const.rb b/bindings/ruby/unicorn_gem/lib/unicorn/arm64_const.rb
index 424de0528e..f7f29f62b2 100644
--- a/bindings/ruby/unicorn_gem/lib/unicorn/arm64_const.rb
+++ b/bindings/ruby/unicorn_gem/lib/unicorn/arm64_const.rb
@@ -268,12 +268,13 @@ module Unicorn
 # pseudo registers
 	UC_ARM64_REG_PC = 260
 	UC_ARM64_REG_CPACR_EL1 = 261
+	UC_ARM64_REG_ESR = 262
 
 # thread registers
-	UC_ARM64_REG_TPIDR_EL0 = 262
-	UC_ARM64_REG_TPIDRRO_EL0 = 263
-	UC_ARM64_REG_TPIDR_EL1 = 264
-	UC_ARM64_REG_ENDING = 265
+	UC_ARM64_REG_TPIDR_EL0 = 263
+	UC_ARM64_REG_TPIDRRO_EL0 = 264
+	UC_ARM64_REG_TPIDR_EL1 = 265
+	UC_ARM64_REG_ENDING = 266
 
 # alias registers
 	UC_ARM64_REG_IP1 = 215
diff --git a/include/unicorn/arm64.h b/include/unicorn/arm64.h
index 586d12da53..71de627bb6 100644
--- a/include/unicorn/arm64.h
+++ b/include/unicorn/arm64.h
@@ -282,6 +282,8 @@ typedef enum uc_arm64_reg {
 
     UC_ARM64_REG_CPACR_EL1,
 
+    UC_ARM64_REG_ESR,			// exception syndrome register
+
     //> thread registers
     UC_ARM64_REG_TPIDR_EL0,
     UC_ARM64_REG_TPIDRRO_EL0,
diff --git a/qemu/target-arm/unicorn_aarch64.c b/qemu/target-arm/unicorn_aarch64.c
index 76e580b5a8..a51fa6971b 100644
--- a/qemu/target-arm/unicorn_aarch64.c
+++ b/qemu/target-arm/unicorn_aarch64.c
@@ -79,6 +79,9 @@ int arm64_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int co
                 case UC_ARM64_REG_CPACR_EL1:
                     *(uint32_t *)value = ARM_CPU(uc, mycpu)->env.cp15.c1_coproc;
                     break;
+	        case UC_ARM64_REG_ESR:
+                    *(uint32_t *)value = ARM_CPU(uc, mycpu)->env.exception.syndrome;
+                    break;
                 case UC_ARM64_REG_TPIDR_EL0:
                     *(int64_t *)value = ARM_CPU(uc, mycpu)->env.cp15.tpidr_el0;
                     break;