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| 1 | +/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd |
| 2 | + * |
| 3 | + * Redistribution and use in source and binary forms, with or without |
| 4 | + * modification, are permitted provided that the following conditions are met: |
| 5 | + * 1. Redistributions of source code must retain the above copyright |
| 6 | + * notice, this list of conditions and the following disclaimer. |
| 7 | + * 2. Redistributions in binary form must reproduce the above copyright |
| 8 | + * notice, this list of conditions and the following disclaimer in the |
| 9 | + * documentation and/or other materials provided with the distribution. |
| 10 | + * |
| 11 | + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND |
| 12 | + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, |
| 13 | + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 14 | + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 15 | + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR |
| 16 | + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| 17 | + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
| 18 | + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| 19 | + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 20 | + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 21 | + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
| 22 | + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 23 | + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 24 | + */ |
| 25 | +#include <rtthread.h> |
| 26 | +#include <rtdevice.h> |
| 27 | +#include "riscv_io.h" |
| 28 | +#include "board.h" |
| 29 | +#include "ioremap.h" |
| 30 | +#include <rtdbg.h> |
| 31 | +#include <stdbool.h> |
| 32 | +#include "sysctl_clk.h" |
| 33 | +#include "drv_pwm.h" |
| 34 | +#include <sys/ioctl.h> |
| 35 | +static struct rt_device_pwm kd_pwm; |
| 36 | +kd_pwm_t *reg_pwm; |
| 37 | + |
| 38 | +static int check_channel(int channel) |
| 39 | +{ |
| 40 | + if (channel < 0 || channel > 5) |
| 41 | + { |
| 42 | + LOG_E("channel %d is not valid\n", channel); |
| 43 | + return -RT_ERROR; |
| 44 | + } |
| 45 | + return channel; |
| 46 | +} |
| 47 | + |
| 48 | +static int pwm_start(kd_pwm_t *reg, int channel) |
| 49 | +{ |
| 50 | + int ret; |
| 51 | + ret = check_channel(channel); |
| 52 | + if (ret < 0) |
| 53 | + return ret; |
| 54 | + |
| 55 | + if (channel > 2) |
| 56 | + { |
| 57 | + reg = (kd_pwm_t *)((void*)reg + 0x40); |
| 58 | + } |
| 59 | + reg->pwmcfg |= (1 << 12); //default always mode |
| 60 | + return ret; |
| 61 | +} |
| 62 | + |
| 63 | +static int pwm_stop(kd_pwm_t *reg, int channel) |
| 64 | +{ |
| 65 | + int ret; |
| 66 | + ret = check_channel(channel); |
| 67 | + if (ret < 0) |
| 68 | + return ret; |
| 69 | + |
| 70 | + if (channel > 2) |
| 71 | + { |
| 72 | + reg = (kd_pwm_t *)((void*)reg + 0x40); |
| 73 | + } |
| 74 | + reg->pwmcfg &= ~(1 << 12); |
| 75 | + |
| 76 | + return ret; |
| 77 | +} |
| 78 | + |
| 79 | +static rt_err_t kd_pwm_get(kd_pwm_t *reg, rt_uint8_t channel, struct rt_pwm_configuration *configuration) |
| 80 | +{ |
| 81 | + int ret; |
| 82 | + uint64_t pulse, period; |
| 83 | + uint32_t pwm_pclock, pwmscale; |
| 84 | + |
| 85 | + ret = check_channel(channel); |
| 86 | + if (ret < 0) |
| 87 | + return ret; |
| 88 | + |
| 89 | + pwm_pclock = sysctl_clk_get_leaf_freq(SYSCTL_CLK_PWM_PCLK_GATE); |
| 90 | + |
| 91 | + if (channel > 2) |
| 92 | + reg = (kd_pwm_t *)((void*)reg + 0x40); |
| 93 | + |
| 94 | + pwmscale = reg->pwmcfg & 0xf; |
| 95 | + pwm_pclock >>= pwmscale; |
| 96 | + period = reg->pwmcmp0; |
| 97 | + period = period * NSEC_PER_SEC / pwm_pclock; |
| 98 | + pulse = *((®->pwmcmp1) + (channel % 3)); |
| 99 | + pulse = pulse * NSEC_PER_SEC / pwm_pclock; |
| 100 | + |
| 101 | + configuration->period = period; |
| 102 | + configuration->pulse = pulse; |
| 103 | + |
| 104 | + return RT_EOK; |
| 105 | +} |
| 106 | + |
| 107 | +static int kd_pwm_set(kd_pwm_t *reg, int channel, struct rt_pwm_configuration *configuration) |
| 108 | +{ |
| 109 | + int ret; |
| 110 | + uint64_t pulse, period, pwmcmpx_max; |
| 111 | + uint32_t pwm_pclock, pwmscale = 0; |
| 112 | + |
| 113 | + ret = check_channel(channel); |
| 114 | + if (ret < 0) |
| 115 | + return ret; |
| 116 | + |
| 117 | + pwm_pclock = sysctl_clk_get_leaf_freq(SYSCTL_CLK_PWM_PCLK_GATE); |
| 118 | + pulse = (uint64_t)configuration->pulse * pwm_pclock / NSEC_PER_SEC; |
| 119 | + period = (uint64_t)configuration->period * pwm_pclock / NSEC_PER_SEC; |
| 120 | + if (pulse > period) |
| 121 | + return -RT_EINVAL; |
| 122 | + |
| 123 | + if (channel > 2) |
| 124 | + reg = (kd_pwm_t *)((void*)reg + 0x40); |
| 125 | + |
| 126 | + /* 计算占空比 */ |
| 127 | + pwmcmpx_max = (1 << 16) - 1; |
| 128 | + if (period > ((1 << (15 + 16)) - 1LL)) |
| 129 | + return -RT_EINVAL; |
| 130 | + |
| 131 | + while ((period >> pwmscale) > pwmcmpx_max) |
| 132 | + pwmscale++; |
| 133 | + if (pwmscale > 0xf) |
| 134 | + return -RT_EINVAL; |
| 135 | + |
| 136 | + reg->pwmcfg |= (1 << 9); //default always mode |
| 137 | + reg->pwmcfg &= (~0xf); |
| 138 | + reg->pwmcfg |= pwmscale; //scale |
| 139 | + reg->pwmcmp0 = (period >> pwmscale); |
| 140 | + *((®->pwmcmp1) + (channel % 3)) = reg->pwmcmp0 - (pulse >> pwmscale); |
| 141 | + |
| 142 | + return RT_EOK; |
| 143 | +} |
| 144 | + |
| 145 | +static rt_err_t kd_pwm_control(struct rt_device_pwm *device, int cmd, void *arg) |
| 146 | +{ |
| 147 | + struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg; |
| 148 | + rt_uint32_t channel = 0; |
| 149 | + int ret; |
| 150 | + |
| 151 | + kd_pwm_t *reg = (kd_pwm_t *)(device->parent.user_data); |
| 152 | + channel = configuration->channel; |
| 153 | + |
| 154 | + switch (cmd) |
| 155 | + { |
| 156 | + case PWM_CMD_ENABLE: |
| 157 | + case KD_PWM_CMD_ENABLE: |
| 158 | + ret = pwm_start(reg, channel); |
| 159 | + if (ret < 0) |
| 160 | + return -RT_ERROR; |
| 161 | + else |
| 162 | + return RT_EOK; |
| 163 | + case PWM_CMD_DISABLE: |
| 164 | + case KD_PWM_CMD_DISABLE: |
| 165 | + ret = pwm_stop(reg, channel); |
| 166 | + if (ret < 0) |
| 167 | + return -RT_ERROR; |
| 168 | + else |
| 169 | + return RT_EOK; |
| 170 | + case PWM_CMD_SET: |
| 171 | + case KD_PWM_CMD_SET: |
| 172 | + kd_pwm_set(reg, channel, configuration); |
| 173 | + break; |
| 174 | + case PWM_CMD_GET: |
| 175 | + case KD_PWM_CMD_GET: |
| 176 | + kd_pwm_get(reg, channel, configuration); |
| 177 | + break; |
| 178 | + default: |
| 179 | + return -RT_EINVAL; |
| 180 | + } |
| 181 | + |
| 182 | + return RT_EOK; |
| 183 | +} |
| 184 | + |
| 185 | +static struct rt_pwm_ops drv_ops = |
| 186 | +{ |
| 187 | + kd_pwm_control |
| 188 | +}; |
| 189 | + |
| 190 | +int rt_hw_pwm_init(void) |
| 191 | +{ |
| 192 | + reg_pwm = (kd_pwm_t *)rt_ioremap((void *)PWM_BASE_ADDR, PWM_IO_SIZE); |
| 193 | + kd_pwm.ops = &drv_ops; |
| 194 | + rt_device_pwm_register(&kd_pwm, "pwm", &drv_ops, (void *)reg_pwm); |
| 195 | +#ifndef RT_FASTBOOT |
| 196 | + rt_kprintf("pwm driver register OK\n"); |
| 197 | +#endif |
| 198 | + return RT_EOK; |
| 199 | +} |
| 200 | +INIT_DEVICE_EXPORT(rt_hw_pwm_init); |
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