|
| 1 | +/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd |
| 2 | + * |
| 3 | + * Redistribution and use in source and binary forms, with or without |
| 4 | + * modification, are permitted provided that the following conditions are met: |
| 5 | + * 1. Redistributions of source code must retain the above copyright |
| 6 | + * notice, this list of conditions and the following disclaimer. |
| 7 | + * 2. Redistributions in binary form must reproduce the above copyright |
| 8 | + * notice, this list of conditions and the following disclaimer in the |
| 9 | + * documentation and/or other materials provided with the distribution. |
| 10 | + * |
| 11 | + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND |
| 12 | + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, |
| 13 | + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 14 | + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 15 | + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR |
| 16 | + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| 17 | + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
| 18 | + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| 19 | + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 20 | + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 21 | + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
| 22 | + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 23 | + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 24 | + */ |
| 25 | + |
| 26 | +#ifndef __SYSCTL_BOOT_H__ |
| 27 | +#define __SYSCTL_BOOT_H__ |
| 28 | + |
| 29 | +#include <stdint.h> |
| 30 | +#include <stdbool.h> |
| 31 | +// #include "platform.h" |
| 32 | + |
| 33 | +#define SYSCTL_BASE_ADDR 0x91100000 |
| 34 | +#define SYSCTL_BOOT_BASE_ADDR (SYSCTL_BASE_ADDR + 0x2000) /* SYSCTL_BASE_ADDR=0x9110_0000 */ |
| 35 | + |
| 36 | +typedef struct pll { |
| 37 | + volatile uint32_t cfg0; |
| 38 | + volatile uint32_t cfg1; |
| 39 | + volatile uint32_t ctl; |
| 40 | + volatile uint32_t state; |
| 41 | +} pll_t; |
| 42 | + |
| 43 | +typedef struct sysctl_boot { |
| 44 | + pll_t pll[4]; |
| 45 | + volatile uint32_t soc_boot_ctl; /* 0x40 */ |
| 46 | + volatile uint32_t reserved0[7]; /* 0x44 0x48 0x4c 0x50 0x54 0x58 0x5c*/ |
| 47 | + volatile uint32_t soc_glb_rst; /* 0x60 */ |
| 48 | + volatile uint32_t soc_rst_tim; /* 0x64 */ |
| 49 | + volatile uint32_t soc_slp_tim; /* 0x68 */ |
| 50 | + volatile uint32_t soc_slp_ctl; /* 0x6c */ |
| 51 | + volatile uint32_t clk_stable_tim; /* 0x70 */ |
| 52 | + volatile uint32_t cpu_wakeup_tim; /* 0x74 */ |
| 53 | + volatile uint32_t soc_wakeup_src; /* 0x78 */ |
| 54 | + volatile uint32_t cpu_wakeup_cfg; /* 0x7c */ |
| 55 | + volatile uint32_t timer_pause_ctl; /* 0x80 */ |
| 56 | + volatile uint32_t reserved1[3]; /* 0x84 0x88 0x8c */ |
| 57 | + volatile uint32_t sysctl_int0_raw; /* 0x90 */ |
| 58 | + volatile uint32_t sysctl_int0_en; /* 0x94 */ |
| 59 | + volatile uint32_t sysctl_int0_state; /* 0x98 */ |
| 60 | + volatile uint32_t reserved2; /* 0x9c */ |
| 61 | + volatile uint32_t sysctl_int1_raw; /* 0xa0 */ |
| 62 | + volatile uint32_t sysctl_int1_en; /* 0xa4 */ |
| 63 | + volatile uint32_t sysctl_int1_state; /* 0xa8 */ |
| 64 | + volatile uint32_t reserved3; /* 0xac */ |
| 65 | + volatile uint32_t sysctl_int2_raw; /* 0xb0 */ |
| 66 | + volatile uint32_t sysctl_int2_en; /* 0xb4 */ |
| 67 | + volatile uint32_t sysctl_int2_state; /* 0xb8 */ |
| 68 | + volatile uint32_t reserved4[17]; /* 0xbc 0xc0-0xcc 0xd0-0xdc 0xe0-0xec 0xf0-0xfc*/ |
| 69 | + volatile uint32_t cpu0_hart_rstvec; /* 0x100 */ |
| 70 | + volatile uint32_t cpu1_hart_rstvec; /* 0x104 */ |
| 71 | + volatile uint32_t reserved5[4]; /* 0x108 0x10c 0x110 0x114 */ |
| 72 | + volatile uint32_t soc_sleep_mask; /* 0x118 */ |
| 73 | +} sysctl_boot_t; |
| 74 | + |
| 75 | + |
| 76 | +// 参考k230 TRM |
| 77 | +typedef enum |
| 78 | +{ |
| 79 | + SYSCTL_BOOT_NORFLASH = 0, |
| 80 | + SYSCTL_BOOT_NANDFLASH = 1, |
| 81 | + SYSCTL_BOOT_EMMC = 2, |
| 82 | + SYSCTL_BOOT_SDCARD = 3, |
| 83 | + SYSCTL_BOOT_MAX, |
| 84 | +}sysctl_boot_mode_e; |
| 85 | + |
| 86 | +sysctl_boot_mode_e sysctl_boot_get_boot_mode(void); |
| 87 | +bool sysctl_boot_get_otp_bypass(void); |
| 88 | +void sysctl_boot_set_pll_lock(void); |
| 89 | +void sysctl_boot_set_spi2axi(void); |
| 90 | +void sysctl_boot_reset_soc(void); |
| 91 | + |
| 92 | +int sysctl_boot_read_is_boot_wakeup(void); |
| 93 | +void sysctl_boot_soc_sleep_ctl(void); |
| 94 | + |
| 95 | +#endif |
0 commit comments