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Commit 1104866

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Fix more warnings
1 parent 14d7f87 commit 1104866

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4 files changed

+20
-11
lines changed

4 files changed

+20
-11
lines changed

src/control.rs

Lines changed: 11 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -18,16 +18,19 @@ impl HrControltExt for HRTIM_COMMON {
1818
fn hr_control(self, #[allow(unused_variables)] rcc: &mut Rcc) -> HrTimOngoingCalibration {
1919
let common = unsafe { &*HRTIM_COMMON::ptr() };
2020

21-
unsafe {
22-
#[cfg(feature = "stm32g4")]
23-
let rcc_ptr = &*stm32::RCC::ptr();
21+
let rcc_ptr = {
22+
#[cfg(feature = "stm32g4")] unsafe {
23+
&*stm32::RCC::ptr()
24+
}
2425

25-
#[cfg(feature = "stm32f3")]
26-
let rcc_ptr = &mut rcc.apb2;
26+
#[cfg(feature = "stm32f3")] {
27+
&mut rcc.apb2
28+
}
29+
};
2730

28-
<HRTIM_COMMON as Enable>::enable(rcc_ptr);
29-
<HRTIM_COMMON as Reset>::reset(rcc_ptr);
30-
}
31+
<HRTIM_COMMON as Enable>::enable(rcc_ptr);
32+
<HRTIM_COMMON as Reset>::reset(rcc_ptr);
33+
3134

3235
// Start calibration procedure
3336
common

src/external_event.rs

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -195,6 +195,7 @@ pub struct SourceBuilder<const N: u8, const IS_FAST: bool> {
195195
filter_bits: u8,
196196
}
197197

198+
#[cfg(feature = "stm32g4")]
198199
impl<const N: u8, const IS_FAST: bool> SourceBuilder<N, IS_FAST> {
199200
unsafe fn new(src_bits: u8) -> Self {
200201
Self {

src/fault.rs

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -50,6 +50,7 @@ pub unsafe trait FaultSource: Copy {
5050
const ENABLE_BITS: u8;
5151
}
5252

53+
#[cfg(feature = "stm32g4")]
5354
pub struct SourceBuilder<I> {
5455
_input: I,
5556
src_bits: u8,
@@ -61,6 +62,7 @@ pub struct SourceBuilder<I> {
6162
filter_bits: u8,
6263
}
6364

65+
#[cfg(feature = "stm32g4")]
6466
impl<I> SourceBuilder<I> {
6567
unsafe fn new(input: I, src_bits: u8) -> Self {
6668
SourceBuilder {

src/lib.rs

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -142,6 +142,7 @@ pub enum InterleavedMode {
142142
/// NOTE: Affects Cr1
143143
Dual,
144144

145+
#[cfg(feature = "hrtim_v2")]
145146
/// Triple interleaved mode
146147
///
147148
/// Automatically force
@@ -154,6 +155,7 @@ pub enum InterleavedMode {
154155
/// using CMP2 (dual channel dac trigger and triggered-half modes).
155156
Triple,
156157

158+
#[cfg(feature = "hrtim_v2")]
157159
/// Quad interleaved mode
158160
///
159161
/// Automatically force
@@ -241,10 +243,12 @@ macro_rules! hrtim_finalize_body {
241243
},
242244
};
243245

244-
let (half, intlvd) = match $this.interleaved_mode {
246+
let (half, _intlvd) = match $this.interleaved_mode {
245247
InterleavedMode::Disabled => (false, 0b00),
246248
InterleavedMode::Dual => (true, 0b00),
249+
#[cfg(feature = "hrtim_v2")]
247250
InterleavedMode::Triple => (false, 0b01),
251+
#[cfg(feature = "hrtim_v2")]
248252
InterleavedMode::Quad => (false, 0b10),
249253
};
250254

@@ -267,8 +271,7 @@ macro_rules! hrtim_finalize_body {
267271
#[cfg(feature = "hrtim_v2")]
268272
tim.cr().modify(|_r, w| unsafe {
269273
// Interleaved mode
270-
#[cfg(feature = "hrtim_v2")]
271-
w.intlvd().bits(intlvd)
274+
w.intlvd().bits(_intlvd)
272275
});
273276

274277
$(

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