More cleanup of G4 and H7 examples

Author: usbalbin

examples/stm32g4/flt-comp.rs

@@ -4,6 +4,7 @@
 /// Example showcasing the use of the HRTIM peripheral together with a comparator to implement a current fault.
 /// Once the comparator input exceeds the reference set by the DAC, the output is forced low and put into a fault state.
 use cortex_m_rt::entry;
+use fugit::ExtU32 as _;
 use panic_probe as _;
 use stm32_hrtim::{
     compare_register::HrCompareRegister,
@@ -18,7 +19,7 @@ use stm32g4xx_hal::{
     adc::AdcClaim,
     comparator::{self, ComparatorExt, ComparatorSplit},
     dac::{Dac3IntSig1, DacExt, DacOut},
-    delay::SYSTDelayExt,
+    delay::{DelayExt as _, SYSTDelayExt},
     gpio::GpioExt,
     pwr::PwrExt,
     rcc::{self, RccExt},
@@ -88,8 +89,8 @@ fn main() -> ! {
         .polarity(hal::pwm::Polarity::ActiveHigh)
         .finalize(&mut hr_control);
 
-    // ...with a prescaler of 4 this gives us a HrTimer with a tick rate of 1.2GHz
-    // With max the max period set, this would be 1.2GHz/2^16 ~= 18kHz...
+    // ...with a prescaler of 4 this gives us a HrTimer with a tick rate of 960MHz
+    // With max the max period set, this would be 960MHz/2^16 ~= 15kHz...
     let prescaler = Pscl4;
 
     let pin_a = gpioa.pa8;
@@ -126,15 +127,15 @@ fn main() -> ! {
     out1.enable_rst_event(&cr1); // Set low on compare match with cr1
     out1.enable_set_event(&timer); // Set high at new period
     cr1.set_duty(timer.get_period() / 3);
-    //unsafe {((HRTIM_COMMON::ptr() as *mut u8).offset(0x14) as *mut u32).write_volatile(1); }
+
     out1.enable();
     timer.start(&mut hr_control.control);
 
     defmt::info!("Started");
 
     loop {
         for _ in 0..5 {
-            //delay.delay(500_u32.millis());
+            delay.delay(500_u32.millis());
             defmt::info!(
                 "State: {:?}, comp: {}, is_fault_active: {}, pc1: {}",
                 out1.get_state(),

examples/stm32g4/flt.rs

@@ -84,23 +84,15 @@ fn main() -> ! {
         .pwm_advanced(pin_a)
         .prescaler(prescaler)
         .period(0xFFFF)
-        //.with_fault_source(fault_source1)
-        //.with_fault_source(fault_source2)
-        .with_fault_source(fault_source3) // Set fault source
-        //.with_fault_source(fault_source4)
-        //.with_fault_source(fault_source5)
-        //.with_fault_source(fault_source6)
+        .with_fault_source(fault_source3)
         .fault_action1(FaultAction::ForceInactive)
         .fault_action2(FaultAction::ForceInactive)
-        // alternated every period with one being
-        // inactive and the other getting to output its wave form
-        // as normal
         .finalize(&mut hr_control);
 
     out.enable_rst_event(&cr1); // Set low on compare match with cr1
     out.enable_set_event(&timer); // Set high at new period
     cr1.set_duty(timer.get_period() / 3);
-    //unsafe {((HRTIM_COMMON::ptr() as *mut u8).offset(0x14) as *mut u32).write_volatile(1); }
+
     out.enable();
     timer.start(&mut hr_control.control);
 

examples/stm32g4/master.rs

@@ -107,8 +107,8 @@ fn main() -> ! {
     defmt::info!("Running");
 
     loop {
-        // Step frequency from 18kHz to about 180kHz(half of that when only looking at one pin)
-        for i in 1..10 {
+        // Step frequency from 15kHz to about 146kHz(half of that when only looking at one pin)
+        for i in 1..=10 {
             let new_period = u16::MAX / i;
 
             mcr1.set_duty(new_period / 3);

examples/stm32h7/hrtim.rs

@@ -36,9 +36,7 @@ fn main() -> ! {
     // since HRTIMSEL is set to take the HRTIM's clock directly from the core clock. The
     // stm32h7 devices' HRTIM does not have a DLL, also leading to an effective HRTIM
     // frequency of 240MHz...
-    let ccdr = rcc
-        .sys_ck(240.MHz())
-        .freeze(pwrcfg, &dp.SYSCFG);
+    let ccdr = rcc.sys_ck(240.MHz()).freeze(pwrcfg, &dp.SYSCFG);
 
     // Acquire the GPIO peripherals. This also enables the clock for
     // the GPIOs in the RCC register.