|
| 1 | +#![no_std] |
| 2 | +#![no_main] |
| 3 | + |
| 4 | +use cortex_m_rt::entry; |
| 5 | +use panic_probe as _; |
| 6 | +use stm32_hrtim::{ |
| 7 | + compare_register::HrCompareRegister, control::HrControltExt, output::HrOutput, timer::HrTimer, |
| 8 | + HrParts, HrPwmAdvExt, Pscl4, |
| 9 | +}; |
| 10 | +use stm32h7xx_hal::{ |
| 11 | + delay::DelayExt, |
| 12 | + gpio::GpioExt, |
| 13 | + pwr::PwrExt, |
| 14 | + rcc::{self, RccExt}, |
| 15 | + stm32::{CorePeripherals, Peripherals}, |
| 16 | +}; |
| 17 | + |
| 18 | +use fugit::{ExtU32, RateExtU32 as _}; |
| 19 | + |
| 20 | +#[entry] |
| 21 | +fn main() -> ! { |
| 22 | + defmt::info!("Initializing..."); |
| 23 | + |
| 24 | + let dp = Peripherals::take().expect("cannot take peripherals"); |
| 25 | + let cp = CorePeripherals::take().expect("cannot take core"); |
| 26 | + |
| 27 | + // Constrain and Freeze power |
| 28 | + let pwr = dp.PWR.constrain(); |
| 29 | + let pwrcfg = pwr.freeze(); |
| 30 | + |
| 31 | + // Constrain and Freeze clock |
| 32 | + let rcc = dp.RCC.constrain(); |
| 33 | + let ccdr = rcc.sys_ck(320.MHz()).freeze(pwrcfg, &dp.SYSCFG); |
| 34 | + |
| 35 | + // Acquire the GPIO peripherals. This also enables the clock for |
| 36 | + // the GPIOs in the RCC register. |
| 37 | + let gpioa = dp.GPIOA.split(ccdr.peripheral.GPIOA); |
| 38 | + |
| 39 | + // Get the delay provider. |
| 40 | + let mut delay = cp.SYST.delay(ccdr.clocks); |
| 41 | + |
| 42 | + // ...with a prescaler of 4 this gives us a HrTimer with a tick rate of 960MHz |
| 43 | + // With max the max period set, this would be 960MHz/2^16 ~= 15kHz... |
| 44 | + let prescaler = Pscl4; |
| 45 | + |
| 46 | + let pin_a = gpioa.pa8; |
| 47 | + let pin_b = gpioa.pa9; |
| 48 | + |
| 49 | + // . . . . |
| 50 | + // . 30% . . . |
| 51 | + // ---- . .---- . |
| 52 | + //out1 | | . | | . |
| 53 | + // | | . | | . |
| 54 | + // -------- ---------------------------- -------------------- |
| 55 | + // . .---- . .---- |
| 56 | + //out2 . | | . | | |
| 57 | + // . | | . | | |
| 58 | + // ------------------------ ---------------------------- ---- |
| 59 | + // . . . . |
| 60 | + // . . . . |
| 61 | + let (hr_control, ..) = dp |
| 62 | + .HRTIM_COMMON |
| 63 | + .hr_control(ccdr.peripheral.HRTIM) |
| 64 | + .wait_for_calibration(); |
| 65 | + let mut hr_control = hr_control.constrain(); |
| 66 | + |
| 67 | + let HrParts { |
| 68 | + mut timer, |
| 69 | + mut cr1, |
| 70 | + out: (mut out1, mut out2), |
| 71 | + .. |
| 72 | + } = dp |
| 73 | + .HRTIM_TIMA |
| 74 | + .pwm_advanced((pin_a, pin_b), &mut rcc) |
| 75 | + .prescaler(prescaler) |
| 76 | + .period(0xFFFF) |
| 77 | + .push_pull_mode(true) // Set push pull mode, out1 and out2 are |
| 78 | + // alternated every period with one being |
| 79 | + // inactive and the other getting to output its wave form |
| 80 | + // as normal |
| 81 | + .finalize(&mut hr_control); |
| 82 | + |
| 83 | + out1.enable_rst_event(&cr1); // Set low on compare match with cr1 |
| 84 | + out2.enable_rst_event(&cr1); |
| 85 | + |
| 86 | + out1.enable_set_event(&timer); // Set high at new period |
| 87 | + out2.enable_set_event(&timer); |
| 88 | + |
| 89 | + out1.enable(); |
| 90 | + out2.enable(); |
| 91 | + |
| 92 | + loop { |
| 93 | + // Step frequency from 18kHz to about 180kHz(half of that when only looking at one pin) |
| 94 | + for i in 1..10 { |
| 95 | + let new_period = u16::MAX / i; |
| 96 | + |
| 97 | + cr1.set_duty(new_period / 3); |
| 98 | + timer.set_period(new_period); |
| 99 | + |
| 100 | + delay.delay(500_u32.millis()); |
| 101 | + } |
| 102 | + } |
| 103 | +} |
0 commit comments